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Search: Posts Made By: milindas
Forum: VHDL 01-11-2010
Replies: 1
Views: 788
Posted By milindas
Smile easier assignment of the vector in testbench

Hi,
I have a small question. In my VHDL code i have a 32 bit std_logic_vector.
ex: data_in: in std_logic_vector (31 downto 0);

suppose in my test bench i need to assign some value to it. i need...
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