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Search: Posts Made By: debayan_p
Forum: VHDL 09-21-2010
Replies: 2
Views: 686
Posted By debayan_p
Well there is an easier way I guess.........I...

Well there is an easier way I guess.........I don't know whether it will serve your purpose!

Use an external gated-clock for your design! For this you need not invoke the analog unit; the clk...
Forum: VHDL 09-13-2010
Replies: 2
Views: 558
Posted By debayan_p
Sure you can do it!! But I am not very sure...

Sure you can do it!!

But I am not very sure if it can be done with the same process!

If you do the writing and the readings in different processes, then it can be done! Just chk it out, I am...
Forum: VHDL 08-03-2010
Replies: 10
Views: 36,991
Posted By debayan_p
I guess using IEEE official libraries is better...

I guess using IEEE official libraries is better coz they will not cause synthesis problems at a latter stage.

There are many synthesis tools, all of them don't follow the same libraries!!
...
Forum: VHDL 08-03-2010
Replies: 2
Views: 654
Posted By debayan_p
Hey, just think in very simple terms! ...

Hey, just think in very simple terms!

Suppose I design a 4:1 MUX with VHDL/Verilog. Now this design would be clock-less...right?

Of course Synopsys DA or some FPGA tools would allow you to do...
Forum: VHDL 07-26-2010
Replies: 1
Views: 662
Posted By debayan_p
27 views and no replies......... Someone...

27 views and no replies.........

Someone please throw some light on it!!!
Forum: VHDL 07-19-2010
Replies: 1
Views: 662
Posted By debayan_p
Need the architecture of a Barrel Processor

Hello friends,

I am helping one of my friends to design a barrel-processor.

I have searched the internet and haven't found any block-level specification or the architecture of a barrel...
Forum: VHDL 11-13-2009
Replies: 1
Views: 618
Posted By debayan_p
Ok, I found my answer ! Max operating...

Ok, I found my answer !

Max operating frequency of my circuit = clock_period - slack

8)
Forum: VHDL 11-12-2009
Replies: 1
Views: 618
Posted By debayan_p
Question on "slack"

I am using Synopsys Design Compiler to generate reports for my design. Now i have a question here.

My system clock is 20 Mhz, or 50 ns!

I want to know/calculate what is the max. frequency at...
Forum: VHDL 11-06-2009
Replies: 1
Views: 612
Posted By debayan_p
Wink Take the VHDL book by Douglas Perry and solve the...

Take the VHDL book by Douglas Perry and solve the exercises given at the end of each chapter. That will solve ur problem !
Forum: VHDL 09-24-2009
Replies: 1
Views: 653
Posted By debayan_p
Hi, Which compiler are u using ? My ModelSim...

Hi,

Which compiler are u using ? My ModelSim has never given me such an error !

If u use clk='1' then the sensitivity list will be triggered only when the signal value is true '1'.

But if u...
Forum: VHDL 09-15-2009
Replies: 2
Views: 813
Posted By debayan_p
Lightbulb For complex digital designs, I do something like...

For complex digital designs, I do something like this......


I keep each digital block as a separate entity....they have their own clock, n_reset, input & output signals.

Have test-benches for...
Forum: VHDL 09-08-2009
Replies: 3
Views: 3,171
Posted By debayan_p
see the following website.....it had a stepper...

see the following website.....it had a stepper motor thread 8 months ago...

vlsibank(dot)com
Forum: VHDL 09-03-2009
Replies: 1
Views: 553
Posted By debayan_p
No one has nothing to say....no remote...

No one has nothing to say....no remote suggestions ??
Forum: VHDL 08-31-2009
Replies: 1
Views: 553
Posted By debayan_p
Suggestion for Frame Handler Design

Hi all,

I am developing the hardware for the Data Link Layer of the IO-Link communication protocol (slave device) !

I want to implement the Frame Handler using the state-machines concept !
...
Forum: VHDL 08-24-2009
Replies: 2
Views: 2,530
Posted By debayan_p
It is difficult to suggest something in this way....

It is difficult to suggest something in this way. I do not have the overview of the whole design !
Forum: VHDL 08-24-2009
Replies: 2
Views: 491
Posted By debayan_p
"Please give me the way i can produce the...

"Please give me the way i can produce the continuous display on seven
segment."

-----------------------------------------

U may be messing up with the refresh rate of the displays.


Check...
Forum: VHDL 08-11-2009
Replies: 14
Views: 1,628
Posted By debayan_p
@ thread started....

P.S - I have not read all the replies. I have read only the original post and 2 subsequent replies and answering accordingly !!

Why don't u use a tri-state buffer between the Core & the RAM ?...
Forum: VHDL 06-30-2009
Replies: 0
Views: 729
Posted By debayan_p
BAUD rate problem

Hi all,

I am designing an UART Tx-Rx. It will have all the features such as overflow, frame error, register empty, etc indicators. In addition I'll be using oversampling for bit detection and...
Forum: VHDL 06-23-2009
Replies: 1
Views: 649
Posted By debayan_p
sorry, forgot to mention my email ID ...

sorry, forgot to mention my email ID

Interested people can contact me at debayanpaul(at-the-rate-of)yahoo(dot)com
Forum: VHDL 06-23-2009
Replies: 1
Views: 649
Posted By debayan_p
Lightbulb IO-Link Slave Device IP Core

Hi all,

IO–Link is used predominantly in an industrial environment in automated production for linking sensors and actuators and is a point-to-point protocol(it is not a field bus system or a...
Forum: VHDL 06-23-2009
Replies: 1
Views: 538
Posted By debayan_p
ha ha ha ha......U have copied the code from...

ha ha ha ha......U have copied the code from asic-world.com -- Memory design section !!

Instead of doing such things 1st clear ur fundamentals. Take any good VHDL book and go through it. Study for...
Forum: VHDL 06-17-2009
Replies: 1
Views: 474
Posted By debayan_p
for i 0 to 2 loop cnt <= cnt +1; end loop; ...

for i 0 to 2 loop
cnt <= cnt +1;
end loop;

The above is ok if you declare 'cnt' as a variable. Is it necessary to declare it as a signal ?

Later when ur looping is complete you can saaign the...
Forum: VHDL 06-17-2009
Replies: 2
Views: 849
Posted By debayan_p
Where have u been saving ur .vhd files ? By...

Where have u been saving ur .vhd files ?

By default it is saved under the 'work' directory. So when the 'Start Simulation' window opens, the 1st expandable library u'll see is work. Under this u...
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