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Forum: VHDL 02-15-2008
Replies: 1
Views: 624
Posted By neilmac
others and aggregates...

If I have a signal called jim, which is a vector of, say, 7 downto 0 and in a clk'd process I make these assignments to this signal for a given a case condition :

when condition_true

-- set...
Forum: VHDL 02-07-2008
Replies: 2
Views: 595
Posted By neilmac
Do constants need to be in anon-clk'd process's sensitivity list if they are i/ps

If Ive got a proces like this, which is basically combitorial, do constants need to be in the sensitivity list?

I think not.

In my case the constant is defined in another package, not within...
Forum: VHDL 01-11-2008
Replies: 2
Views: 658
Posted By neilmac
Ok - all my own bad work. Was a delta issue and...

Ok - all my own bad work. Was a delta issue and now resolved...nothing to do with modelsim.
Forum: VHDL 01-11-2008
Replies: 2
Views: 658
Posted By neilmac
Im thinking this is a simulation time delta delay...

Im thinking this is a simulation time delta delay issue?
Forum: VHDL 01-10-2008
Replies: 2
Views: 658
Posted By neilmac
Modelsim and signal transitions on clk edges

RTL simulation in modelsim. I have one block that outputs an ack signal and data that changes on a clock edge. Another block has this ack and data as an input (registered inputs). Now when the ack...
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