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Search: Posts Made By: lokesh_boddu
Forum: VHDL 12-13-2006
Replies: 0
Views: 660
Posted By lokesh_boddu

hello designers

i am working on virtex2VPro FPGA, the bit file generated is put in the QPROM from which the FPGA downloads and gets configured on Powerup.

my question here is
is there any way...
Forum: VHDL 11-24-2006
Replies: 30
Views: 14,428
Posted By lokesh_boddu
Hi Bert Thanks for you rules,i am getting...

Hi Bert

Thanks for you rules,i am getting them in use,they are very much useful.

could you please explain me how to write test benches in a very efficient considering at least few worst...
Forum: VHDL 11-15-2006
Replies: 16
Views: 717
Posted By lokesh_boddu
mysticlol wrote: > Is Gated clock approach...

mysticlol wrote:
> Is Gated clock approach advisable for this kind of requirement?
> en <= enA_1 and enA_2;
> process (clk, nrst, en)
> if nrst = '0' then
> A <= '0';
> elsif...
Forum: VHDL 11-08-2006
Replies: 0
Views: 752
Posted By lokesh_boddu
FPGA design


could you please explain me about the "bonded IOBs"
i am working on FPGA ,xilinx ISE 8.1 .

the target board is virtex 2vpro and it has 156 IBOs
i am able to synthesis my design with few...
Forum: VHDL 10-31-2006
Replies: 0
Views: 686
Posted By lokesh_boddu
Synthesis problem


i am working FPGAs,i have synthesized a design using xilinx ISE 8.1and i have a final report like below

Device utilization summary:

Selected Device :...
Forum: VHDL 10-18-2006
Replies: 0
Views: 447
Posted By lokesh_boddu
Power analysis


I am Lokesh,
could any one guid me on Power analysis
i am using VHDL,and Xiling tool 8.1 version
it would be great if any document is provided to me

Thanks in advance
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