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Forum: VHDL 09-23-2008
Replies: 3
Views: 1,169
Posted By Steff
Hi ecenus, std_logic_vector is the right...

Hi ecenus,

std_logic_vector is the right type for your design.

If you want to transmit this vector you have two different approaches:

1. sequentiell design:
You have one pin and you have to...
Forum: VHDL 09-22-2008
Replies: 3
Views: 1,169
Posted By Steff
Hi, if a one stays for an error, you can do...

Hi,

if a one stays for an error, you can do this:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;

signal s_error_vec : std_logic_vector(0 to 16);
Forum: VHDL 09-22-2008
Replies: 1
Views: 571
Posted By Steff
Hi, if I understand you right, you can solve...

Hi,

if I understand you right, you can solve this problem with a generate construct.
Your code would be like this:



type t_slv_array is array(natural range <>) of std_logic_vector(31 downto...
Forum: VHDL 09-19-2008
Replies: 4
Views: 747
Posted By Steff
Hy, it is of course possible having an array...

Hy,

it is of course possible having an array length of 1, but you have to map the value by (index) name not by position. Therefore you must write:

createLevels : levels_array_t(0 to 0) := (0...
Forum: VHDL 09-17-2008
Replies: 5
Views: 789
Posted By Steff
Your welcome!

Your welcome!
Forum: VHDL 09-16-2008
Replies: 8
Views: 13,691
Posted By Steff
Hy, I agree with tarmopalm. I would...

Hy,

I agree with tarmopalm.

I would also say that your number represents -0.0078125(dec).

Short explanation:

Your number is 1.111 1111(bin).
Your scaling_factor then is...
Forum: VHDL 09-15-2008
Replies: 1
Views: 1,080
Posted By Steff
Hy, doesn't matter which kind of synthesis...

Hy,

doesn't matter which kind of synthesis tool you take.
All these tools are not able to synthesis non-static numbers of type real.

If you want to synthesis random patterns like the procedure...
Forum: VHDL 09-15-2008
Replies: 5
Views: 789
Posted By Steff
hy mreiser, one more question: Have you...

hy mreiser,

one more question:
Have you ever compiled this code or occures the fatal error at this time?
(Because your code has compile errors.)

Here a version of your function without...
Forum: VHDL 09-12-2008
Replies: 5
Views: 789
Posted By Steff
Hy, can you give me the type declarations of...

Hy,

can you give me the type declarations of the both arrays:

channel_selection_array and
channel_output_array

thanx, Steff
Forum: VHDL 09-08-2008
Replies: 3
Views: 546
Posted By Steff
Your welcome!

Your welcome!
Forum: VHDL 09-08-2008
Replies: 3
Views: 546
Posted By Steff
Hi, if you have typeless vector like "00"...

Hi,

if you have typeless vector like "00" and you want to convert it to a concret type you have to do it in the following way:

type'("00")

sum <= unsigned'("00"&NBC(0))+
...
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