Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Search Forums > Search Results

Showing results 1 to 5 of 5
Search took 0 seconds.
Search: Posts Made By: Roya
Forum: VHDL 08-20-2009
Replies: 1
Views: 473
Posted By Roya
Multi-source

hi, every one
i have problem in my design. I use 2 signals :one for hand-shake and one for acknowledgment . in the process1 the hand_shake signal should be one and the ACK signal should be zero, on...
Forum: VHDL 07-27-2009
Replies: 4
Views: 1,436
Posted By Roya
I understood that these simultaneous assignments...

I understood that these simultaneous assignments are not possible so i try another way: I make the clk, 3 times faster .so when rising edge of the faster clk is comming for the third time , all the...
Forum: VHDL 07-27-2009
Replies: 4
Views: 1,436
Posted By Roya
First i want to thank you so much since you give...

First i want to thank you so much since you give me a pluperfect and quaint point(state machine) .you're right, i need to do some reading on VHDL. I am a beginner in VHDL and I'm going to learn it...
Forum: VHDL 07-26-2009
Replies: 4
Views: 1,436
Posted By Roya
signal assignment and Delta delay

Hi,
can any one help me about this , the following signal assignment is in the process:

Red<=dout;
temp <= temp-"00000001";
Green<=dout;
temp <= temp-"00000001";
Blue<=dout;
temp <=...
Forum: Hardware 07-02-2009
Replies: 0
Views: 1,963
Posted By Roya
coregen-->single port block memory

Hi, i got a single port block memory from Xilinx coregen and I initialized it by .coe file. can I read this Rom through this command R<=dout?!
is it clear to read an output port? if not how could I...
Showing results 1 to 5 of 5

 
Forum Jump


Advertisments