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Search: Posts Made By: surpriya.7
Forum: VHDL 04-29-2009
Replies: 4
Views: 1,347
Posted By surpriya.7
Please try this: entity clk_div is ...

Please try this:

entity clk_div is
Port ( clk : in STD_LOGIC;
div: in STD_LOGIC_VECTOR(3 downto 0);
div_clk : out STD_LOGIC);
end clk_div;

architecture Behavioral of...
Forum: VHDL 04-17-2009
Replies: 10
Views: 1,113
Posted By surpriya.7
Hi John, I think the 1st debugging step here...

Hi John,
I think the 1st debugging step here is with the patch of code below:
I think the patch should prodice clk_synch as the output. You are using 'clk_divider' but apparently not using it to...
Forum: VHDL 04-16-2009
Replies: 4
Views: 687
Posted By surpriya.7
Hi zhfs, i think your code is not showing the...

Hi zhfs,
i think your code is not showing the errors you are saying it gets...rather im getting a diff set of errors...

Compiling vhdl file "D:/Projects/codes/sample codes/trial/try2.vhd" in...
Forum: VHDL 03-25-2009
Replies: 2
Views: 1,562
Posted By surpriya.7
Thanks for your help jeppe.... i got the...

Thanks for your help jeppe....
i got the difference! :)
Forum: VHDL 03-25-2009
Replies: 2
Views: 1,562
Posted By surpriya.7
difference between inertial and transport delay

Hello All,
I am currently perplexed understanding the difference between inertial and transport delay.
Well, a definition that I caught at another forum goes like this:
"The main...
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