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Forum: VHDL 08-13-2012
Replies: 1
Views: 1,280
Posted By imed
Check this link it seams to discuss the same...

Check this link it seams to discuss the same issue:
http://forums.xilinx.com/t5/Simulation-and-Verification/Simulate-COREGEN-in-ModelSim/td-p/28722
hope that helps...
Forum: VHDL 08-10-2012
Replies: 0
Views: 524
Posted By imed
Ko counter in Test Bench

Hi!
What's the best way to handle KO number in test benches?
- manually increment a counter inside TB code?
- do all the checks through a procedure which increment the err_cnt as a shared variable...
Forum: VHDL 08-08-2012
Replies: 3
Views: 585
Posted By imed
that's why: my procedure must have signal name...

that's why:
my procedure must have signal name of type string as an additional input :(
proc_check(test, "test checking", '0') for example :(
Forum: VHDL 08-08-2012
Replies: 3
Views: 585
Posted By imed
well, It turns out the same guy, @Jonathan...

well,
It turns out the same guy, @Jonathan Bromley, posted a reply for the same question, 6 years later (2011) and said that there is no direct way to do that ! :)...
Forum: VHDL 08-08-2012
Replies: 2
Views: 482
Posted By imed
Hi! I don't see why don't you use ascii code in...

Hi!
I don't see why don't you use ascii code in hexdecimal.
Forum: VHDL 08-07-2012
Replies: 3
Views: 585
Posted By imed
The aim of all this for me is to write a...

The aim of all this for me is to write a procedure that checks if a signal value is equal to a given expected value and print a message starting with the name of signal:
proc_check(signal signal_in,...
Forum: VHDL 08-06-2012
Replies: 3
Views: 585
Posted By imed
Question attribute signal name in procedure

Hi !
My question was asked before (2005):
The answer given by @Jonathan Bromley was to try the following:
The problem is that I tried that and I got:
# simple_name = s...
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