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Search: Posts Made By: smurfjavel
Forum: VHDL 10-08-2009
Replies: 5
Views: 1,087
Posted By smurfjavel
Creating synthesis error depending on generic values.

At least Synplify Pro sets a Synthesis error if you generate a process with a wait statement.

I tried this which works both for synthesis and for simulation, might be helpful if you would like to...
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