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Search: Posts Made By: jerryo
Forum: VHDL 01-16-2010
Replies: 1
Views: 788
Posted By jerryo
Hi, A statement like this is an option ...

Hi,
A statement like this is an option
data <= (0 => '1', 1 => '1', 2 => '1', 4 => '1', 8 => '1', others => '0');
You can assign specific bits in a vector and set the others to a default.
...
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