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Search: Posts Made By: Vindog67
Forum: VHDL 10-12-2011
Replies: 0
Views: 962
Posted By Vindog67
Exclamation Port map with if and process

Hi , I am currently working on FIR filter on vhdl on FPGA,(and yes i suck on programming)
Just wondering is it possible to do the if loop with port map?

here is my code. it keep telling me there...
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