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Search: Posts Made By: flymolo
Forum: VHDL 09-24-2011
Replies: 3
Views: 1,913
Posted By flymolo
I think you will get maximum performance with...

I think you will get maximum performance with Xilinx Core generator.
http://www.xilinx.com/support/documentation/ip_documentation/addsub_ds214.pdf
If you want to keep it parameric, try to add input...
Forum: VHDL 07-29-2011
Replies: 3
Views: 1,093
Posted By flymolo
yeah when i copy the code from my editor tabs are...

yeah when i copy the code from my editor tabs are missing in the post. I use editor option to change tabs into spaces before posting.
Forum: VHDL 07-20-2011
Replies: 3
Views: 2,720
Posted By flymolo
Hmm,I think the efficiency of one-hot comes from...

Hmm,I think the efficiency of one-hot comes from the fact that You don't need to compare if other bits are zero. Assuming the mux input is an array type and array size matches select_signal size...
Forum: VHDL 07-14-2011
Replies: 1
Views: 1,183
Posted By flymolo
This is VHDL language forum, not a DSP forum ;) ...

This is VHDL language forum, not a DSP forum ;)
http://www.dspguide.com/pdfbook.htm
Chapter 14
Forum: VHDL 07-08-2011
Replies: 3
Views: 1,217
Posted By flymolo
Hey. I had some free time today and i came up...

Hey. I had some free time today and i came up with this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity smp_avg is
generic(
IN_WIDTH ...
Forum: VHDL 07-06-2011
Replies: 3
Views: 1,217
Posted By flymolo
How many samples you want to average? Does the...

How many samples you want to average? Does the number of samples to average changes in runtime or do you want to pass it as generic? Is this going to be implemented in FPGA?
In general i would use...
Forum: VHDL 06-20-2011
Replies: 2
Views: 1,079
Posted By flymolo
You can do it in many ways. I guess the most...

You can do it in many ways. I guess the most straightforward is:
'1' & '0' & CS0 & '1' & '0' & '0' & CLK & '1' & '0'
you can group constants:
b"10" & CS0 & b"100" & CLK & b"10"
Forum: VHDL 06-08-2011
Replies: 1
Views: 1,440
Posted By flymolo
If you want to preserve design hierarchy through...

If you want to preserve design hierarchy through synthesis and place and route use XST -keep_hierarchy switch (you can acces this throug GUI: select top level entry, right click on Synthesize XST ->...
Forum: VHDL 06-02-2011
Replies: 2
Views: 4,765
Posted By flymolo
These synthesis warnings can be ignored as long...

These synthesis warnings can be ignored as long as it is intended that these signals are tied to a constant values. What is the problem with the design? Does it work?
Forum: VHDL 06-02-2011
Replies: 3
Views: 2,667
Posted By flymolo
Hi Can you please provide some code? What is...

Hi
Can you please provide some code? What is the width of a signal for the result.
I dont think you will get better result by coding it by hand. Synthesizers nowadays will infer constant...
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