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Forum: VHDL 11-21-2011
Replies: 3
Views: 964
Posted By Obtice
thanks, first solution worked, Library...

thanks,
first solution worked,


Library IEEE;
use ieee.std_logic_1164.all;

Entity counter is
port
(
Forum: VHDL 11-21-2011
Replies: 3
Views: 964
Posted By Obtice
Counter with initial value

Hi,
I have a counter written in VHDL :


Library IEEE;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;

Entity counter is
port
Forum: VHDL 11-13-2011
Replies: 12
Views: 1,348
Posted By Obtice
and what's wrong with this statement : Reg(...

and what's wrong with this statement :
Reg( conv_integer( sd)) <= Result when Rising_edge( Clk) else Reg( conv_integer( sd));

It says "signal parameter in a subprogram is not supported"

...
Forum: VHDL 11-13-2011
Replies: 12
Views: 1,348
Posted By Obtice
what if I want to set initial value for reg array...

what if I want to set initial value for reg array ?
like this (in front of signal regs:reg;)
but i don't know how !
I have deleted first process .


Library ieee;
use ieee.std_logic_1164.all;...
Forum: VHDL 11-13-2011
Replies: 12
Views: 1,348
Posted By Obtice
thanks ...... this is my final project but...

thanks ......

this is my final project
but I got this error :
signal Reg multiple sources. (64 error for this, 8*8 )
what can I do ? :(((


Library ieee;
use ieee.std_logic_1164.all;
Forum: VHDL 11-11-2011
Replies: 12
Views: 1,348
Posted By Obtice
thanks alot, really thanks, Could you explain...

thanks alot,
really thanks,
Could you explain this part :
Result_internal <= Reg( conv_integer( Sel1)) + 5;
and why two selects ?

thanks in advance ...
Forum: VHDL 11-11-2011
Replies: 12
Views: 1,348
Posted By Obtice
thanks again, I think I must use sequential...

thanks again,
I think I must use sequential code, :(
I want something like this, but the working one, not this :D (just want to show what I mean)


R0 <= Y when Sel="000" else
R1 <= Y...
Forum: VHDL 11-11-2011
Replies: 12
Views: 1,348
Posted By Obtice
ok, tnx, but another problem, I want a 3 to 8...

ok, tnx,
but another problem,
I want a 3 to 8 decoder. concurrently . if sel="000" result will be stored in R0, if sel ="001" result will be stored in R1 and so on .
what can I do ? I can't use...
Forum: VHDL 11-10-2011
Replies: 12
Views: 1,348
Posted By Obtice
help on choosing a strategy

hi everybody,
I want to perform 3 actions sequentially. First, I want to mux to choosing one of the eight registers, then I want to perform an operation on this, then I want to store result in...
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