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Search: Posts Made By: boysr2003
Forum: Computer Support 12-18-2006
Replies: 0
Views: 607
Posted By boysr2003
Compatibility of the PLX PCI 9656 card with the PCI X slot

Hi,
my name is Yassir Boukhriss. I would like to know if anyone knows if the PLX Technology PCI 9656 card is compatible with any PCI X slot used in any HP or Dell servers.
Thanks
Yassir Boukhriss
Forum: VHDL 12-02-2006
Replies: 4
Views: 30,836
Posted By boysr2003
FFT in VHDL

Hi,
my name is Yassir Boukhriss. You can use the core generator available in ISE foundation, and instantiate that in your top level code.
Yassir Boukhriss
Forum: VHDL 12-01-2006
Replies: 4
Views: 8,869
Posted By boysr2003
How to calculate amplitude and phase of a A/D signal

Hi,
my name is Yassir Boukhriss,
i think the amplitude depends on the precision of the A/D. if it was a 12 bit A/D the amplitude would go between -2^11 to 2^11. As far as frequency goes, you can do...
Forum: VHDL 12-01-2006
Replies: 12
Views: 3,705
Posted By boysr2003
Comment on VHDL vs. System Generator

Hi,
my name is Yassir Boukhriss, from my experience, System Generator is not intended to replace VHDL coding. It's a convenient tool to generate VHDL code if you can match the timing constraints of...
Forum: VHDL 12-01-2006
Replies: 2
Views: 770
Posted By boysr2003
Matlab and VHDL

Hi,
my name is Yassir Boukhriss. I am doing the same thing with a different board that has a xilinx fpga. I guess, you need to write a c program to read data from the channel that has the signal of...
Forum: C++ 11-29-2006
Replies: 0
Views: 2,294
Posted By boysr2003
Client socket program in c

Hi,
my name Yassir Boukhriss. I was wondering if anyone recommends writing a client socket program in c rather than in java.
Thanks
Yassir Boukhriss
Forum: VHDL 11-29-2006
Replies: 0
Views: 738
Posted By boysr2003
How to meet timing constraints in an FPGA

Hi, my name is Yassir Boukhriss. I am using System generator from Xilinx. I have succesfully integrated a system generator design into a top level VHDL code of a digital receiver running on Virtex...
Forum: VHDL 11-27-2006
Replies: 0
Views: 587
Posted By boysr2003
how to meet timing constraints in an FPGA

Hi, my name is Yassir Boukhriss. I have succesfully integrated a system generator design into a top level code of a digital receiver. The simulink system period is a fraction of the periods of all...
Forum: VHDL 07-27-2006
Replies: 0
Views: 998
Posted By boysr2003
Importing a Xilinx system generator design into a bigger system

Hi my name is Yassir Boukhriss, and i am currently using Xilinx
System Generator. I generated the vhdl code for my system generator
design and included the generated ngc file in my top level code...
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