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 Showing results 1 to 7 of 7 Search took 0 seconds. Search: Posts Made By: Jerrie85
 Forum: VHDL 08-24-2006 Replies: 2 Views: 542 Posted By Jerrie85 i'm sure someone's got this before...does anyone... i'm sure someone's got this before...does anyone know? pleasee help
 Forum: VHDL 08-24-2006 Replies: 2 Views: 542 Posted By Jerrie85 i'm sure someone's got this before...does anyone... i'm sure someone's got this before...does anyone know? pleasee help
 Forum: VHDL 08-22-2006 Replies: 10 Views: 812 Posted By Jerrie85 Hello, a few points to note: a)... Hello, a few points to note: a) this problem looks purely combinational to me; if so, why do you want processes on the clk edge? its a waste of a flip flop b)i dont seem to quite...
 Forum: VHDL 08-21-2006 Replies: 2 Views: 542 Posted By Jerrie85 No clock signals found in design... Whenever i synthesize i top level block in xilinx, i get this msg, "No clock signals found in design", so i dont get information about the clock speed or clock delay; this is wierd since i have a...
 Forum: VHDL 08-21-2006 Replies: 2 Views: 482 Posted By Jerrie85 why dont u just transmit_clk <=... why dont u just transmit_clk <= ~receive_serial_clock; this is just straight inverter, combination logic
 Forum: VHDL 08-19-2006 Replies: 1 Views: 678 Posted By Jerrie85 when you multiply two 32 bit numbers, the... when you multiply two 32 bit numbers, the resultant is always 2 * 32 bits long at max 64 bits long ... u can test this out by doing (2^32 - 1)(2^32-1) = (2^64 - 2^33 - 2) i multiplied the two...
 Forum: VHDL 08-18-2006 Replies: 0 Views: 897 Posted By Jerrie85 assign statement verilog Hello folks, this is most prob a newb question, but in vhdl, i can assign values to vectors like, valueout <= value1 when addr=addr2 else value3 when...
 Showing results 1 to 7 of 7

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