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Forum: VHDL 02-11-2010
Replies: 2
Views: 515
Posted By Ricewind
Thank you very much, it works fine : D

Thank you very much, it works fine : D
Forum: VHDL 02-11-2010
Replies: 2
Views: 515
Posted By Ricewind
Multiple loop GENERATE

Hi, I need to make a Generate statement depending on 2 variables.

I have tried to code it this way but it does not work:

registro8bits: FOR i IN 1 TO numcol
FOR j IN 0 TO numfil GENERATE...
Forum: VHDL 01-28-2010
Replies: 3
Views: 5,233
Posted By Ricewind
Error again... HDL simulation model...

Error again...

HDL simulation model compilation failed.
ERROR:HDLCompiler:435 - "xlisim_System68.vhd" Line 1805: Formal senh1 is not declared
ERROR:HDLCompiler:432 - "xlisim_System68.vhd" Line...
Forum: VHDL 01-28-2010
Replies: 3
Views: 5,233
Posted By Ricewind
Noob doubt about components

Hallo. I am currently starting a project in VHDL and I am trying to learn a bit for getting the first steps...

I have been trying to do a simple component and to compile and simulate it through...
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