FPGA - Offset in/out values
 

Hello,

I'm working on a VHDL project using Xilinx ISE 14.1 and I'm facing some troubles with Timing Constraints.

As far as the Period constraint is asked there's no problem, I understand it; what's bugging me is how to choose the offset in and out constraints: I've never done it before and I don't know why I should care about them too.

So far I have tried randomly, reading what the Timing Report says (like "the minimum allowable offset in is...") and acting accordingly, but I'm not fully satisfied.

Any help?