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Obtice 11-10-2011 05:19 PM

help on choosing a strategy
 
hi everybody,
I want to perform 3 actions sequentially. First, I want to mux to choosing one of the eight registers, then I want to perform an operation on this, then I want to store result in another register. could I write my code concurrently ?
What can I do ? without using process.

jeppe 11-11-2011 09:55 AM

Seems to be a "strait forward" problem - just write the concurrent code :)

Obtice 11-11-2011 03:14 PM

Quote:

Originally Posted by jeppe (Post 4395803)
Seems to be a "strait forward" problem - just write the concurrent code :)

ok, tnx,
but another problem,
I want a 3 to 8 decoder. concurrently . if sel="000" result will be stored in R0, if sel ="001" result will be stored in R1 and so on .
what can I do ? I can't use when because my outputs are different . As you can see.

jeppe 11-11-2011 08:22 PM

Could this be a part of the solution?

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity eksample1 is
    Port ( Sel : in  STD_LOGIC_VECTOR (2 downto 0);
          Result : out  STD_LOGIC_VECTOR (7 downto 0));
end eksample1;

architecture Behavioral of eksample1 is
  signal Y: STD_LOGIC_VECTOR (7 downto 0);
begin
  Y <= "00000001" when Sel="000" else
        "00000010" when Sel="001" else
        "00000100" when Sel="010" else
        "00001000" when Sel="011" else
        "00010000" when Sel="100" else
        "00100000" when Sel="101" else
        "01000000" when Sel="110" else
        "10000000";  -- Sel="111" as default
       
-- with Sel select
-- Y <= "00000001" when "000",
--      "00000010" when "001",
--      "00000100" when "010",
        -- and so on
--      "10000000" when others;   

end Behavioral;

If you want to use the same registers for both data sources and destination for data must you use a Clock signal as well in your design.

Obtice 11-11-2011 09:25 PM

Quote:

Originally Posted by jeppe (Post 4395927)
If you want to use the same registers for both data sources and destination for data must you use a Clock signal as well in your design.

thanks again,
I think I must use sequential code, :(
I want something like this, but the working one, not this :D (just want to show what I mean)

Code:

  R0 <= Y when Sel="000" else
  R1 <= Y when Sel="001" else
  R2 <= Y when Sel="010" else
  R3 <= Y when Sel="011" else
  R4 <= Y when Sel="100" else
  R5 <= Y when Sel="101" else
  R6 <= Y when Sel="110" else
  R7 <= Y when sel="111";

one another thing(sorry for this dummy questions) :
I have eight 8-bit registers in my circuit. How can I implement them ? signal ? variable ? or in one component ? (this registers are : R0, R1, .... in decoder)

jeppe 11-11-2011 09:58 PM

This could perhaps be a solution - however will the mux be "hidden" in the index
like Reg[ index given by Sel1]

----------------------------------------------------------------------------------
Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity eksample2 is
    Port ( Sel1,Sel2 : in  STD_LOGIC_VECTOR (2 downto 0);
          Clk : in  STD_LOGIC;
          Result : out  STD_LOGIC_VECTOR (7 downto 0));
end eksample2;

architecture Behavioral of eksample2 is
  type Regs is array(0 to 7) of STD_LOGIC_VECTOR (7 downto 0);
  signal Reg: Regs;
  signal Result_internal: STD_LOGIC_VECTOR (7 downto 0);
begin
  Result_internal <=  Reg( conv_integer( Sel1)) + 5;  -- Select a register with Sel1 and add 5

  Result <= Result_internal;

  -- Write back the result to a register selected with Sel2
  Reg( conv_integer( Sel2)) <= Result_internal when Rising_edge( Clk) else  Reg( conv_integer( Sel2)); 
end Behavioral;


Obtice 11-11-2011 10:30 PM

Quote:

Originally Posted by jeppe (Post 4395949)
This could perhaps be a solution - however will the mux be "hidden" in the index
like Reg[ index given by Sel1]

----------------------------------------------------------------------------------
Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity eksample2 is
    Port ( Sel1,Sel2 : in  STD_LOGIC_VECTOR (2 downto 0);
          Clk : in  STD_LOGIC;
          Result : out  STD_LOGIC_VECTOR (7 downto 0));
end eksample2;

architecture Behavioral of eksample2 is
  type Regs is array(0 to 7) of STD_LOGIC_VECTOR (7 downto 0);
  signal Reg: Regs;
  signal Result_internal: STD_LOGIC_VECTOR (7 downto 0);
begin
  Result_internal <=  Reg( conv_integer( Sel1)) + 5;  -- Select a register with Sel1 and add 5

  Result <= Result_internal;

  -- Write back the result to a register selected with Sel2
  Reg( conv_integer( Sel2)) <= Result_internal when Rising_edge( Clk) else  Reg( conv_integer( Sel2)); 
end Behavioral;



thanks alot,
really thanks,
Could you explain this part :
Result_internal <= Reg( conv_integer( Sel1)) + 5;
and why two selects ?

thanks in advance ...

jeppe 11-12-2011 09:55 AM

Quote:

Originally Posted by Obtice (Post 4395630)
hi everybody,
I want to perform 3 actions sequentially. First, I want to mux to choosing one of the eight registers, then I want to perform an operation on this, then I want to store result in another register. could I write my code concurrently ?
What can I do ? without using process.

Seems you wanted to choose one register, perform an operation (like + 5) and the store the result in another register - then you will need two select values.

The internal register mostly for debug purposes.

The Conv_integer( Selx ) converts the three bit Selx signal to an integer between 0 and 7. The integer type requered as index for the array.

You could referer to a register 0 with Reg(0) ... 1 with Reg(1) .... 7 with Reg(7) but only for reading.
In order to write must you involve a Rising_edge( Clk) and yes - you properly need some sequential code for this part.

Obtice 11-13-2011 12:40 PM

thanks ......

this is my final project
but I got this error :
signal Reg multiple sources. (64 error for this, 8*8 )
what can I do ? :(((

Code:

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.all;

Entity cpu is
    port( R0, R1, R2, R3, R4, R5, R6, R7: in std_logic_vector(7 downto 0);
          IR: in std_logic_vector(12 downto 0);
          CLK: in std_logic;
          output: out std_logic_vector(7 downto 0));
end cpu;

Architecture cpu of cpu is
    signal BusA, BusB: std_logic_vector(7 downto 0);
    signal SA: std_logic_vector(2 downto 0);
    signal SB: std_logic_vector(2 downto 0);
    signal SD: std_logic_vector(2 downto 0);
    signal OP: std_logic_vector(3 downto 0);
    type Regs is array(0 to 7) of std_logic_vector(7 downto 0);
    signal Reg: Regs;
    signal Result: std_logic_vector(7 downto 0);
Begin
    SA <= IR(12 downto 10);
    SB <= IR(9 downto 7);
    SD <= IR(6 downto 4);
    OP <= IR(3 downto 0);
    process(CLK)
    begin
        if(rising_edge(CLK)) then
            Reg(0) <= R0;
            Reg(1) <= R1;
            Reg(2) <= R2;
            Reg(3) <= R3;
            Reg(4) <= R4;
            Reg(5) <= R5;
            Reg(6) <= R6;
            Reg(7) <= R7;
        end if;
    end process;
    -------------------------------------------
    BusA <= Reg(0) when SA = "000" else
            Reg(1) when SA = "001" else
            Reg(2) when SA = "010" else
            Reg(3) when SA = "011" else
            Reg(4) when SA = "100" else
            Reg(5) when SA = "101" else
            Reg(6) when SA = "110" else
            Reg(7);
    -------------------------------------------
    BusB <= Reg(0) when SB = "000" else
            Reg(1) when SB = "001" else
            Reg(2) when SB = "010" else
            Reg(3) when SB = "011" else
            Reg(4) when SB = "100" else
            Reg(5) when SB = "101" else
            Reg(6) when SB = "110" else
            Reg(7);
    --------------------------------------------
    Result <= BusA + BusB when OP = "0000" else
              BusA - BusB when OP = "0010" else
              BusA XOR BusB when OP = "0011" else
              '0' & BusA(7 downto 1) when OP = "0100" else
              BusA(6 downto 0) & '0' when OP = "0101" else
              BusA(0) & BusA(7 downto 1) when OP = "1010" else
              BusA + BusB;
    --------------------------------------------
    output <= Result;
    process(CLK)
    begin
        if(Falling_edge(CLK)) then
            Reg(conv_integer(SD)) <= Result;
        end if;
    end process;
end cpu;


jeppe 11-13-2011 01:36 PM

Code:

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.all;

Entity cpu is
    port( R0, R1, R2, R3, R4, R5, R6, R7: inout std_logic_vector(7 downto 0);
          IR: in std_logic_vector(12 downto 0);
          CLK: in std_logic;
          output: out std_logic_vector(7 downto 0));
end cpu;

Architecture cpu of cpu is
    signal BusA, BusB: std_logic_vector(7 downto 0);
    signal SA: std_logic_vector(2 downto 0);
    signal SB: std_logic_vector(2 downto 0);
    signal SD: std_logic_vector(2 downto 0);
    signal OP: std_logic_vector(3 downto 0);
    signal Result: std_logic_vector(7 downto 0);
Begin
    SA <= IR(12 downto 10);
    SB <= IR(9 downto 7);
    SD <= IR(6 downto 4);
    OP <= IR(3 downto 0);
    process(CLK)
    begin
    -------------------------------------------
    BusA <= R0 when SA = "000" else
                  R1 when SA = "001" else
                  R2 when SA = "010" else
                  R3 when SA = "011" else
                  R4 when SA = "100" else
                  R5 when SA = "101" else
                  R6 when SA = "110" else
                R7;
    -------------------------------------------
    BusB <= R0 when SB = "000" else
                  R1 when SB = "001" else
                  R2 when SB = "010" else
                R3 when SB = "011" else
                R4 when SB = "100" else
                R5 when SB = "101" else
                R6 when SB = "110" else
                R7;
    --------------------------------------------
    Result <= BusA + BusB when OP = "0000" else
                    BusA - BusB when OP = "0010" else
                    BusA XOR BusB when OP = "0011" else
                    '0' & BusA(7 downto 1) when OP = "0100" else
                    BusA(6 downto 0) & '0' when OP = "0101" else
                    BusA(0) & BusA(7 downto 1) when OP = "1010" else
                    BusA + BusB;
    --------------------------------------------
    output <= Result;
    process(CLK)
    begin
        if(Rising_edge(CLK)) then
            case SD is
                  when "000" => R0 <= Result;
                  when "001" => R1 <= Result;
                  when "010" => R2 <= Result;
                  when "011" => R3 <= Result;
                  when "100" => R4 <= Result;
                  when "101" => R5 <= Result;
                  when "110" => R6 <= Result;
                  when "111" => R7 <= Result;
                  when others => null;
              end case;
        end if;
    end process;
end cpu;

Well try this - (could contian syntaks error - but the principles shoud be ok)
Remember a signal can only have one driver - hence must you only have one process or
concurrent statement which defines its output value:


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