HI. I try to write addition of rational numbers program in vhdl.below program working in RTL design ?.
entity ratpack_rtl is
a : in std_logic;
b : in std logic;
c : out std_logic;
clk : in std_logic);
architecture rtl of ratpack_rtl is
variable a : rational := (5/12);
variable b : rational := (2/3);
c <= a+b;
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