VHDL Program
 

HI. I try to write addition of rational numbers program in vhdl.below program working in RTL design ?.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity ratpack_rtl is
port(
a : in std_logic;
b : in std logic;
c : out std_logic;
clk : in std_logic);
end ratpack_rtl;


architecture rtl of ratpack_rtl is
begin

process(clk,a,b)

begin

variable a : rational := (5/12);
variable b : rational := (2/3);

c <= a+b;

end process;
end rtl;



Regards
Raghu