Port map with if and process
Hi , I am currently working on FIR filter on vhdl on FPGA,(and yes i suck on programming)
Just wondering is it possible to do the if loop with port map?
here is my code. it keep telling me there is syntax error over there
Line 134: Syntax error near "PORT".
Line 139: Syntax error near ";".
Allocate_process : process(clka)
if (index>= 23 ) then
end process Allocate_process;
Multi1_process : process
here>Alloc1:InputX_ROM PORT MAP
clka => clka,
addra => counter,
douta => Input
and here> );
end process Multi1_process;
PLEASE HELP ME
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