Velocity Reviews

Velocity Reviews (
-   VHDL (
-   -   Port map with if and process (

Vindog67 10-12-2011 02:29 PM

Port map with if and process
Hi , I am currently working on FIR filter on vhdl on FPGA,(and yes i suck on programming)
Just wondering is it possible to do the if loop with port map?

here is my code. it keep telling me there is syntax error over there

Line 134: Syntax error near "PORT".
Line 139: Syntax error near ";".

Allocate_process : process(clka)
Multi_Coeff1(index)<= Temp;
if (index>= 23 ) then
SigState(0)<= '1';
end if;
end process Allocate_process;

Multi1_process : process

here>Alloc1:InputX_ROM PORT MAP
clka => clka,
addra => counter,
douta => Input
and here> );
end if;
end process Multi1_process;


All times are GMT. The time now is 08:11 PM.

Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.