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Amish Rughoonundon 06-10-2011 03:53 PM

divide by zero error from XILINX ISE
 
Hi,
I have this code. XILINX ISE Is giving me an error HDLParsers:866
"Division by zero" during synthesis. Why is that? Thanks for the help

Code:

CONSTANT CLOCK_FREQUENCY        : integer := 50000000;      -- Input
clock frequency in hertz

CONSTANT SWITCHING_FREQUENCY    : integer := 400000;        -- date
drive frequency in hertz

CONSTANT CLOCK_END_RAMP_RESET_A            : integer :=
INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/
REAL(CLOCK_FREQUENCY)))-1;


Paul Uiterlinden 06-10-2011 05:10 PM

Re: divide by zero error from XILINX ISE
 
Amish Rughoonundon wrote:

> Hi,
> I have this code. XILINX ISE Is giving me an error HDLParsers:866
> "Division by zero" during synthesis. Why is that? Thanks for the help
>
>
Code:

> CONSTANT CLOCK_FREQUENCY        : integer := 50000000;      -- Input
> clock frequency in hertz
>
> CONSTANT SWITCHING_FREQUENCY    : integer := 400000;        -- date
> drive frequency in hertz
>
> CONSTANT CLOCK_END_RAMP_RESET_A            : integer :=
> INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/
> REAL(CLOCK_FREQUENCY)))-1;
>



I have no idea. One thing I do know: your code looks overcomplicated (to
me).

If I'm not mistaken, the above is identical to:

constant CLOCK_END_RAMP_RESET_A : integer :=
integer(0.5 * real(CLOCK_FREQUENCY) / real(SWITCHING_FREQUENCY)) - 1;

For the rest: I don't have real experience with Xilinx (or any other
synthesizer for that matter).

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

Gabor Sz 06-11-2011 04:06 PM

Re: divide by zero error from XILINX ISE
 
On Jun 10, 11:53*am, Amish Rughoonundon <amishrughoonun...@gmail.com>
wrote:
> Hi,
> *I have this code. XILINX ISE Is giving me an error HDLParsers:866
> "Division by zero" during synthesis. Why is that? Thanks for the help
>
>
Code:

> CONSTANT CLOCK_FREQUENCY * * * *: integer := 50000000; * * *-- Input
> clock frequency in hertz
>
> CONSTANT SWITCHING_FREQUENCY * *: integer := 400000; * * * *-- date
> drive frequency in hertz
>
> CONSTANT CLOCK_END_RAMP_RESET_A * * * * * * : integer :=
> INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/
> REAL(CLOCK_FREQUENCY)))-1;
>



I'm going to take a wild guess that Xilinx is taking 1/CLOCK_FREQUENCY
and converting it to integer zero, instead of using a real for the
final
divide operation. Perhaps using Paul's simplified version will fix
the problem. The other possibility is that Xilinx's real format has
an underflow for 1/50000000. This might happen if they don't use
enough bits when dividing the mantissas for the intermediate result.
Either way it could be called a bug. IEEE floating point has defined
the temporary precision just for this sort of issue.

-- Gabor


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