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-   -   Incorrect simulation of a shift register in multiplication (http://www.velocityreviews.com/forums/t746720-incorrect-simulation-of-a-shift-register-in-multiplication.html)

 Joseph 04-13-2011 07:00 AM

Incorrect simulation of a shift register in multiplication

Hi all,

I am synthesizing a well known add-shift multiplication routine. I have theMultiplier register Q ,an addition register A and a Carry register C (the carry of the adder) which are concatenated together to give the multiplication results. For the shifting part I am writing the following code:

Q <= A(0) & Q(3 downto 1);
A <= C & A(3 downto 1);

That should perform a right shift in both A and Q. This is being done in a clocked process so registers are being created (that is working). When synthesizing using Xilinx and simulating using ISIM the right shift is being performed but the LSB of Q never has the correct value.

Am I coding it incorrectly in Xilinx?

Regards,

Joseph

 jeppe 04-13-2011 08:37 AM

Hi Joseph

Perhaps should you post some more code - the statements posted seems to be ok.

Regards
Jeppe

 Thomas Stanka 04-13-2011 12:28 PM

Re: Incorrect simulation of a shift register in multiplication

On 13 Apr., 09:00, Joseph <joz...@gmail.com> wrote:
> Q <= A(0) & Q(3 downto 1);
> A <= C & A(3 downto 1);
>
> That should perform a right shift in both A and Q. This is being done in a clocked process so registers are being created (that is working). When synthesizing using Xilinx and simulating using ISIM the right shift is being performed but the LSB of Q never has the correct value.

This code snipplet has to less information. Actually there are plenty
of reasons why a vhdl code simulates different than the synthesis
result of this code. Without further information it is not predictabel
You can not "code it incorrect in Xilinx". But you can easily write
vhdl code which has "misleading" simulation result compared to the
netlist you get after synthesis independend of the used tools.

bye Thomas

 Andy 04-13-2011 02:42 PM

Re: Incorrect simulation of a shift register in multiplication

Not enough info. Are the other bits getting "correct" values? How can
you tell that Q(0) is not getting the "correct" value? (What is the
correct value?)

Andy

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