Velocity Reviews

Velocity Reviews (http://www.velocityreviews.com/forums/index.php)
-   VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)
-   -   new in vhdl - a little question (http://www.velocityreviews.com/forums/t745751-new-in-vhdl-a-little-question.html)

ee1 03-26-2011 08:34 AM

new in vhdl - a little question
 
hey, i am new to vhdl, and i wrote a code for a register (the inpute size should be generic).
the register should have datain, enable, reset, and data out
my question is, how can i know if what i wrote works? i mean i compiled it and did not got errors, but how can i know if its functually works?
i uses modelsim.
here is my code:

library IEEE;
use IEEE.std_logic_1164.all;

entity register is
generic(DATA_WIDTH : integer := 8 );
port(clk, reset, load : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0));
end register;

architecture arc_register of register is
begin
process(reset,clk)
begin
if (reset='1') then
data_out <=(others=>'0');
elsif(clk'event and clk='1')then
if(load = '1') then
data_out<=data_in;
end if;
end if;
end process;
end arc_register;

configuration cfg_register of register is
for arc_register
end for;
end cfg_register;

thanks!

rman123 03-28-2011 08:43 PM

Google, "vhdl testbench" and read about it.


All times are GMT. The time now is 04:57 PM.

Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.