Identifier "adder" does not identify a component declaration.
When I compile my code for a 32 bit adder, I get this error. My code for adder is compiling successfully but testbench is giving error.
Here's my code for testbench:
entity adder_testbench is
architecture behavior of adder_testbench is
signal a_tb: std_logic_vector(31 downto 0);
signal b_tb: std_logic_vector(31 downto 0);
signal sum_tb: std_logic_vector(31 downto 0);
signal co_tb :std_logic ;
signal cin_tb : std_logic;
port (A,B: in std_logic_vector(31 downto 0);
CIN: in std_logic;
S: out std_logic_vector(31 downto 0);
COUT: out std_logic);
uut: Work.adder port map(A => a_tb, B => b_tb, CIN => cin_tb, S => sum_tb, COUT => co_tb);
constant period1: time := 20ns;
wait for period1;
assert ((sum_tb = "11111111111111111111111111111111") and (co_tb ='0'))
report "test failed for combination" severity error;
end process tb1;
Uhm perhaps you need to leave out the Work prefix:
You can either write:
uut: adder port map( ...
which will instantiate the component you have typed in the declarative part of your architecture, or you can write:
uut: entity work.adder port map( ...
Which will directly instantiate the entity. No need to copy the component declaration if you use this style.
You can even specify which architecture you want:
uut: entity work.adder(RTL) port map( ...
|All times are GMT. The time now is 06:07 PM.|
Powered by vBulletin®. Copyright ©2000 - 2013, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.