entire 32 bit two's complement integer range is supported in VHDL?
I'm designing a VHDL testbench for a VHDL module.
I have to generate values to be written into a 32 bit register of my
I decided tu use integer variables to compose my data and than convert them
to std_logic_vector to perform the write operation on the module.
The issue is that I discovered that VHDL
integer range is from -2147483647 to 2147483647,
that is to say 16#80000000# integer is not supported.
Is there any way to work out this limitation without using directly
Thank you in advance for any help
|All times are GMT. The time now is 01:43 AM.|
Powered by vBulletin®. Copyright ©2000 - 2013, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.