How to run simulation in Xilinx 12.1 ISE
I have multiple seperate VHD files for a CPU. How can i run all the files and simulate the design to see the results. Can anyone help me. I have included all files by using add source option. But frm then i dont know how to proceed.
Your multiple VHDL files must be used to form one large design - otherwise can't they be simulated together.
Use structural VHDL or draw a Schematic with your component (VHDL files/modules)
|All times are GMT. The time now is 06:05 PM.|
Powered by vBulletin®. Copyright ©2000 - 2013, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.