Problem with vhdl records
I have a DUT which have records in it
package clk_reset_record_pkg is
type clks is record
clk: std_logic_vector(4 downto 0);
type resets is record
reset: std_logic_vector(4 downto 0);
library ieee; -- Library declaration
entity top is
port(clk_in :in clks;
clk_enable : in std_logic;
Now i want to instatiate this dut in my testbench. Tesbench also have same kind of record.
dut:entity work.top(rtl) port map (clk_in => clk_record,
clk_enable => clk_enable,
reset_in => rst_record,
and also use configuration to replace the instatiation as
configuration tb_cfg_rtl of tb is
for dut: top
use entity work.top1(rtl);
I am getting error
Type mismatch for port "clk_in" in component "top" when binding to entity "top1".
Type mismatch for port "reset_in" in component "top" when binding to entity "top1".
It works fine when used without configuration. Is there some another construct in configuration to handle records type ?
Can some body help on this issue.
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