Need help figuring out how to control this.. edge triggering.
Hi, I'm trying to generate this signal in VHDL(signal out). I have a signal coming in (signal in) that I want to trigger off of on the rising edge, then start a counter with a 20MHz clock (I want some sort of delay that I can control) and then bring it low after the counter/delay is finished.
It's hard for me to figure this out because there are two rising edges I need to trigger off of (clk and signal in, which aren't synced up) and VHDL doesn't agree with anything I've tried. How would you implement this? Its not just the rising edges though, I'm not sure how to control the falling edge then either.
I'm having a lot of trouble coding and understanding VHDL and get stuck on problems like this often, anyone have any good advise?
Clocked Delay Started by Input Signal
Since the input signal is not synchronized with the counter clock you will need to use a "synchronizer" on that signal. A common synchronizer is 2 D flip-flops clocked by, in this case, the counter clock. The D input of the first flilp-flop is connected to the input signal and its Q output is connected to the D input of the second flip-flop. Let's call the output of the second D flip-flop sig_synch. sig_synch will be used to start (enable) the counter. If the counter is a down counter, it can be loaded with a number representing the number of clock periods of delay that you need. You can use a signal delay_done to indicate when the counter has reached the count of zero. delay_done stops the counter. You will then reload the counter and wait for the next sig_synch. I have left out a few details. For example, you want to ensure that sig_synch has gone low before the counter is enabled again or you will start a new delay cycle too soon soon.
I hope this helps. It should get you started anyway. If you get stuck again, come back and I am sure someone here will help you.
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