VHDL Testbench and vcd file generation
 

Hi,

I am working on power analysis of general purpose applications in Quartus-II 9.1. The Model sim was invoked for testbench simulation after compilation of the project in Quartuss-II by using a do script file. The vcd file was generated with do file script as shown below but when I tried to generate vcd file with testbench that reads input from input.txt and put output into output.txt file the vcd does not contain any information.

Question is how to generate vcd file with test bench reading text data files?

Thanks in advance for your help and cooperation in this regards.


# AND_TB.do file generated for test bench reading

vsim AND_TB
add wave -r /*
vcd file AND_TB.vcd
vcd add -r *
force x(0) 0
force x(1) 0
force y(0) 0
force y(1) 0
force clock 0 0
run 100
force clock 1 5, 0 50 -repeat 100
force x(0) 1 5, 0 50 -repeat 200
force x(1) 1 5, 0 50 -repeat 100
force y(0) 1 5, 0 50 -repeat 100
force y(1) 1 5, 0 50 -repeat 150
run 1000
vcd checkpoint
quit –sim

# do file script for the generation of vcd file when testbench reads input from text files.
vsim AND_TB
add wave -r /*
vcd file AND_TB.vcd
vcd add -r /AND_TB/ *
vcd checkpoint
run 200ns

Kind Regards
Tayab