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SameerDS 03-23-2010 05:04 AM

static discrete range in generate statements
 
Hi,

I seem to have hit something that is either a bug in ghdl or a
limitation in my understanding of the LRM. What follows is a list of a
small entity that represents what I need. Analysing this with ghdl
(with or without --std=00) results in the following error:

discrete.vhdl:21:3: range must be a static discrete range

Line 21 is where the generate statement occurs in the code. As far as
I can see, the range in question is globally static, and hence it
should not be a problem. A search on the web threw up some discussions
about a similar situation with types, but not with ports, the way I am
using them here.

library ieee;
use ieee.std_logic_1164.all;

entity discrete is

port (
x : in std_logic_vector;
y : out std_logic_vector);

end discrete;

architecture default_arch of discrete is

alias lx : std_logic_vector(x'length - 1 downto 0) is x;
alias ly : std_logic_vector(y'length - 1 downto 0) is y;

begin -- default_arch

assert x'length /= y'length report "mismatched sizes" severity
error;

gen: for i in lx'high downto lx'low generate
ly(i) <= lx(i);
end generate gen;

end default_arch;

Thanks,
Sameer.
--
http://sameer.sbuddhe.net/

joris 03-23-2010 05:11 PM

Though it isn't too clear from the error it's giving, it seems correct.
The actual problem is that the sizes of x and y aren't known.

You could fix that using generics, like
Code:

entity discrete is
generic( n, m : natural );
port (
x : in std_logic_vector(n - 1 downto 0);
y : out std_logic_vector(m - 1 downto 0));

end discrete;


Paul Uiterlinden 03-23-2010 05:37 PM

Re: static discrete range in generate statements
 
SameerDS wrote:

> Hi,
>
> I seem to have hit something that is either a bug in ghdl or a
> limitation in my understanding of the LRM. What follows is a list of a
> small entity that represents what I need. Analysing this with ghdl
> (with or without --std=00) results in the following error:
>
> discrete.vhdl:21:3: range must be a static discrete range
>
> Line 21 is where the generate statement occurs in the code. As far as
> I can see, the range in question is globally static, and hence it
> should not be a problem. A search on the web threw up some discussions
> about a similar situation with types, but not with ports, the way I am
> using them here.
>


For what it is worth: your code compiles with ModelSim 6.3i and 6.5e.

I don't see any reason why this should not compile. But then again I haven't
delved into the LRM for this particular case.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

SameerDS 03-24-2010 11:45 AM

Re: static discrete range in generate statements
 
On Mar 23, 10:37*pm, Paul Uiterlinden <puit...@notaimvalley.nl> wrote:
>
> For what it is worth: your code compiles with ModelSim 6.3i and 6.5e.
>
> I don't see any reason why this should not compile. But then again I haven't
> delved into the LRM for this particular case.


Thanks, it works for me too on ModelSim 6.3a. I think I should ask the
ghdl community instead. AFAIK, this is allowed by the LRM, but doesn't
work in ghdl.

Sameer.
--
http://sameer.sbuddhe.net/

joris 03-24-2010 04:33 PM

I tested with XST, it doesn't allow it either; It gives this error:

ERROR:Xst:2588 - Port <x> of top entity <discrete> is not constrainted.
ERROR:Xst:2588 - Port <y> of top entity <discrete> is not constrainted.


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