Velocity Reviews - Behavioral model for a two out of five detector

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Behavioral model for a two out of five detector

Hey everyone, I am having trouble writing a behavioral model for a two out of five bit detector. Y is always undefined when I simulate it, what am I doing wrong? Here is the code:

Code:

library ieee;

use ieee.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;



entity two_five is                         -- Begin entity

     port(

       A, B, C, D, E: in std_logic;

       Y: out std_logic

          );

end entity two_five;                       -- End entity

-------------------------------------------------



architecture beh of two_five is            -- Begin architecture

signal sig: std_logic_vector (4 DOWNTO 0);

signal cnt: std_logic_vector (1 downto 0) := "00";

begin

    sig <= A&B&C&D&E;

    process (sig)

      begin

        for i in 0 to 4 loop

          if sig(i) = '1' then

            cnt <= cnt + 1;

          end if;

        if cnt = "10" then--count = 2 then

        Y <= '1';

      else Y <= '0';

      end if;

    end loop;

    end process;

end beh;

possible solutio

Change cnt declaration to variable or try to code using logical equation.

with 5 bit vector, the possible values of less than two 1's are
00000
00001
00010
00100
01000
10000

eq =not( (a.b.c.d.e)+(a.b.c.d.E)+(a.b.c.D.e)+(a.b.C.d.e)+(a .B.c.d.e)+(A.b.c.d.e) )

Quote:

Originally Posted by bigmoe88

Hey everyone, I am having trouble writing a behavioral model for a two out of five bit detector. Y is always undefined when I simulate it, what am I doing wrong? Here is the code:

Code:

library ieee;

use ieee.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;



entity two_five is                         -- Begin entity

     port(

       A, B, C, D, E: in std_logic;

       Y: out std_logic

          );

end entity two_five;                       -- End entity

-------------------------------------------------



architecture beh of two_five is            -- Begin architecture

signal sig: std_logic_vector (4 DOWNTO 0);

signal cnt: std_logic_vector (1 downto 0) := "00";

begin

    sig <= A&B&C&D&E;

    process (sig)

      begin

        for i in 0 to 4 loop

          if sig(i) = '1' then

            cnt <= cnt + 1;

          end if;

        if cnt = "10" then--count = 2 then

        Y <= '1';

      else Y <= '0';

      end if;

    end loop;

    end process;

end beh;

Ok, so I tried that and got the same result, also, Y gets '1' only when there are exactly two out of five are high.

Here is the current code:

Code:

library ieee;

use ieee.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;



entity two_five is                         -- Begin entity

     port(

       A, B, C, D, E: in std_logic;

       Y: out std_logic

          );

end entity two_five;                       -- End entity

-------------------------------------------------



architecture beh of two_five is            -- Begin architecture

signal sig: std_logic_vector (4 DOWNTO 0);

begin

    sig <= A&B&C&D&E;

    process (sig)

      variable count: integer;

      begin

        count := 0;

        for i in 0 to 4 loop

          if sig(i) = '1' then

            count := count + 1;

          end if;

        if count = 2 then

        Y <= '1';

      else Y <= '0';

      end if;

    end loop;

    end process;

end beh;

Hi, I am getting the correct result when I simulate the code. BTW, which synthesis and simulation tools are you using.

Quote:

Originally Posted by bigmoe88

Ok, so I tried that and got the same result, also, Y gets '1' only when there are exactly two out of five are high.

Here is the current code:

Code:

library ieee;

use ieee.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;



entity two_five is                         -- Begin entity

     port(

       A, B, C, D, E: in std_logic;

       Y: out std_logic

          );

end entity two_five;                       -- End entity

-------------------------------------------------



architecture beh of two_five is            -- Begin architecture

signal sig: std_logic_vector (4 DOWNTO 0);

begin

    sig <= A&B&C&D&E;

    process (sig)

      variable count: integer;

      begin

        count := 0;

        for i in 0 to 4 loop

          if sig(i) = '1' then

            count := count + 1;

          end if;

        if count = 2 then

        Y <= '1';

      else Y <= '0';

      end if;

    end loop;

    end process;

end beh;

I am using QuestiaSim-64 6.4c. I am not synthesizing it, I am just simulating it with a force file. Here are the contents of the force file:

force A 0 0, 1 10 ns -repeat 10 ns
force B 0 0, 1 20 ns -repeat 20 ns
force C 0 0, 1 30 ns -repeat 30 ns
force D 0 0, 1 40 ns -repeat 40 ns
force E 0 0, 1 50 ns -repeat 50 ns

Ok, so I got it working finally the other day. I created a new project and copied the code into a new file and it all worked well. Have no idea what caused such odd behavior. Thanks so much for your help.