Component selection in ISE
I want to bind any of the two components (written using VHDL) to the top module and I don't want the other component to be synthesized while synthesizing the top module.
But xilinx ISE synthesize all the components in the top module.
The components are complex than the simple gates considered in example below.
------ code example
-- gatesel is declared in package
If (gatesel=1) generate
a1: andg port map(....);
If (gatesel=2) generate
a1: org port map(....);
If (gatesel=3) generate
a1: xorg port map(....);
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