easier assignment of the vector in testbench
I have a small question. In my VHDL code i have a 32 bit std_logic_vector.
ex: data_in: in std_logic_vector (31 downto 0);
suppose in my test bench i need to assign some value to it. i need to type for all 32 bits.
ex: data_in <= "00000000000000000000000000000000"
i was wondering if there is other easier method, with which i can assign say first 5 bits differently and assign all the others bits by '0' or '1'.
thanks in advance :)
A statement like this is an option
data <= (0 => '1', 1 => '1', 2 => '1', 4 => '1', 8 => '1', others => '0');
You can assign specific bits in a vector and set the others to a default.
With a 32b val, you might want to assign this way:
data <= X"0000_0000";
which is clean and compact, using the hex designator (X).
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