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veevee1 12-11-2009 12:50 PM

VHDL component for counting the amount of leading zeroes
 
hello,

What would be the best way (from fast synthesis point of view) to calculate the amount of leading zeroes from substraction result of two bit vectors.


Is there a way to implement it in more convenient way than described below:

signal A : std_logic_vector(9 downto 0);
signal B : std_logic_vector(9 downto 0);

result <= A - B;


Priority coded comparison:

if result(9) = '0' then

elsif result(8) = '0' then

elsif result(7) = '0' then....

############################

I'm after a solution like this


lead_zeros <= ?

case lead_zeros is
when 0 =>
when 1 =>
when 2 =>


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