Velocity Reviews

Velocity Reviews (http://www.velocityreviews.com/forums/index.php)
-   VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)
-   -   converting std_logic_vector to an integer without sign extension (http://www.velocityreviews.com/forums/t706540-converting-std_logic_vector-to-an-integer-without-sign-extension.html)

Mark 11-25-2009 02:28 PM

converting std_logic_vector to an integer without sign extension
 
I'm trying to elegantly convert a std_logic_vector(upper downto lower)
to an integer without sign extension using ieee.numeric_std with upper
and lower taking on values from 31 to 0 and with upper >= lower. I
cannot seem to find a syntax that doesn't generate truncation
warnings, or relies on doing some comparison.

If I use:

i:= to_integer( signed( slv(upper downto lower)));

I'll get sign extension if upper==lower (which I don't want).

To avoid sign extension, I've tried:

i:= to_integer( signed( '0' & slv(upper downto lower)));

That works great until upper=31, and lower=0---leading to a to_signed
truncation warning (since in this case we're creating a 33-bit vector
and reducing it to a 32-bit integer).

I could just check if upper==lower, and break the conversion into two
cases, but I'm wondering if there's a cleaner, more elegant way of
handling this conversion without warnings.




Kenn Heinrich 11-25-2009 03:28 PM

Re: converting std_logic_vector to an integer without sign extension
 
Mark <marmarjohnson@gmail.com> writes:

> I'm trying to elegantly convert a std_logic_vector(upper downto lower)
> to an integer without sign extension using ieee.numeric_std with upper
> and lower taking on values from 31 to 0 and with upper >= lower. I
> cannot seem to find a syntax that doesn't generate truncation
> warnings, or relies on doing some comparison.
>
> If I use:
>
> i:= to_integer( signed( slv(upper downto lower)));
>
> I'll get sign extension if upper==lower (which I don't want).
>
> To avoid sign extension, I've tried:
>
> i:= to_integer( signed( '0' & slv(upper downto lower)));
>
> That works great until upper=31, and lower=0---leading to a to_signed
> truncation warning (since in this case we're creating a 33-bit vector
> and reducing it to a 32-bit integer).
>
> I could just check if upper==lower, and break the conversion into two
> cases, but I'm wondering if there's a cleaner, more elegant way of
> handling this conversion without warnings.
>
>
>


What's wrong with using unsigned instead of signed?

i:= to_integer( unsigned( slv(upper downto lower)));

- Kenn

--
---------------------------------


Martin Thompson 11-25-2009 03:30 PM

Re: converting std_logic_vector to an integer without sign extension
 
Mark <marmarjohnson@gmail.com> writes:

> I'm trying to elegantly convert a std_logic_vector(upper downto lower)
> to an integer without sign extension using ieee.numeric_std with upper
> and lower taking on values from 31 to 0 and with upper >= lower. I
> cannot seem to find a syntax that doesn't generate truncation
> warnings, or relies on doing some comparison.
>
> If I use:
>
> i:= to_integer( signed( slv(upper downto lower)));
>
> I'll get sign extension if upper==lower (which I don't want).
>
> To avoid sign extension, I've tried:
>
> i:= to_integer( signed( '0' & slv(upper downto lower)));


I think you might be trying too hard :)

How about:
i:= to_integer( unsigned( slv(upper downto lower)));

The *unsigned* type is there for doing, erm, unsigned arithmetic and
conversions :)

That should work for upper==lower as well:

entity testint is
end entity testint;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture a1 of testint is
signal slv : std_logic_vector(1 downto 0) := "10";
signal one,zero : integer;
begin -- architecture a1
check: process is
begin -- process check
one <= to_integer(unsigned(slv(1 downto 1)));
zero <= to_integer(unsigned(slv(0 downto 0)));
wait for 0 ps;
assert one = 1 report "1==1 failure" severity error;
assert zero = 0 report "0==0 failure" severity error;
wait;
end process check;
end architecture a1;

Or did I misunderstand the problem?

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Kenn Heinrich 11-25-2009 03:33 PM

Re: converting std_logic_vector to an integer without sign extension
 
Kenn Heinrich <kwheinri@uwaterloo.ca> writes:

> Mark <marmarjohnson@gmail.com> writes:
>
>> I'm trying to elegantly convert a std_logic_vector(upper downto lower)
>> to an integer without sign extension using ieee.numeric_std with upper
>> and lower taking on values from 31 to 0 and with upper >= lower. I
>> cannot seem to find a syntax that doesn't generate truncation
>> warnings, or relies on doing some comparison.
>>
>> If I use:
>>
>> i:= to_integer( signed( slv(upper downto lower)));
>>
>> I'll get sign extension if upper==lower (which I don't want).
>>
>> To avoid sign extension, I've tried:
>>
>> i:= to_integer( signed( '0' & slv(upper downto lower)));
>>
>> That works great until upper=31, and lower=0---leading to a to_signed
>> truncation warning (since in this case we're creating a 33-bit vector
>> and reducing it to a 32-bit integer).
>>
>> I could just check if upper==lower, and break the conversion into two
>> cases, but I'm wondering if there's a cleaner, more elegant way of
>> handling this conversion without warnings.
>>
>>
>>

>
> What's wrong with using unsigned instead of signed?
>
> i:= to_integer( unsigned( slv(upper downto lower)));
>
> - Kenn


Actually, after a brief re-think, you're sort of hosed in any case.
VHDL only officially defines integers as

type integer is range -2147483648 to 2147483647;

which means you can't represent positive x"FFFFFFFF" = 2^32-1 in
integers to begin with. Implementations *may* support larger but it's
not guaranteed.

- Kenn



--
---------------------------------
Remove NOSPAM from email address.

Mark 11-25-2009 04:36 PM

Re: converting std_logic_vector to an integer without sign extension
 
It doesn't matter to me if FFFF_FFFF is treated as -1 or MAX_INT, just
that all the bits are in there. I'd like to get something as C-like
as possible. Unfortunately, VHDL treats unsigned ints (naturals) as a
subtype of integer, and thus are only 31-bits---while C lets you have
32-bit unsigned integers (long)). No problem I thought, I'll just
treat everything as an integer. Unfortunately, doing so in a terse,
warning-free way doesn't seem possible in VHDL.

I'm coming to the conclusion that I'm not going to be able to do a 1-
liner in VHDL without living with warnings. I want my conversions to
be warning free (even if it still works out), so I'm thinking of going
with the following:

lower := c_field_offset;
upper := lower + c_field_size - 1;

if (2**c_field_size-1) > integer'high then
i := to_integer( signed( slv(upper downto lower)));
else
i := to_integer( unsigned( slv(upper downto lower)));
end if;

5-lines instead of 1---but then that's VHDL

Mark 11-25-2009 04:47 PM

Re: converting std_logic_vector to an integer without sign extension
 
On Nov 25, 9:30*am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Wed, 25 Nov 2009 06:28:01 -0800 (PST), Mark wrote:
> >I'm trying to elegantly convert a std_logic_vector(upper downto lower)
> >to an integer without sign extension using ieee.numeric_std with upper
> >and lower taking on values from 31 to 0 and with upper >= lower. *I
> >cannot seem to find a syntax that doesn't generate truncation
> >warnings, or relies on doing some comparison.

>
> What's wrong with...
> * i := to_integer(unsigned(slv));
>
> It will of course give you warnings if the MSB of a 32-bit SLV
> is set, because VHDL integer cannot represent anything more
> positive than (2**31)-1. *That's tedious, but a fact of life.
> But it should work fine with any slv with between 1 and 31
> bits, and it will also work with 32-bit SLVs provided their
> MSB is zero.
>
> If you want to use signed() so that 32-bit slv's with the MSB
> set will come out as negative integers (yuck) then yes, you have
> a small problem with 1-bit values. *How about packing to 32 bits
> first, and then doing the conversion?
>
> * i := to_integer(
> * * * * *signed(
> * * * * * * std_logic_vector'(31 downto upper+1 => '0') & slv
> * * * * *)
> * * * *);
>
> This *may* give warnings for the null range when upper=31,
> although it's legal VHDL (I'm pretty sure).
>
> Finally, why not write a custom function instead of trying to
> inline the ghastly mess?
> * function to_uint(v: std_logic_vector) return integer is
> * begin
> * * if v'length = 0 then
> * * * return 0;
> * * elsif v'length = 1 then
> * * * return to_integer(unsigned(v));
> * * else
> * * * return to_integer(signed(v));
> * * end if;
> * end;
>
> The function also provides you with a convenient place
> to report application-specific errors and so forth.
> But most of all it allows you to hide the kruft.
> --
> Jonathan Bromley, Verification Engineer
>
> Verilab *www.THAT_COMPANY.com
> * end;


Gave

i := to_integer( signed( std_logic_vector'(31 downto upper+1 =>
'0') & slv(upper downto lower) ));

a try. Got:

** Warning: [3] test.vhd(25): (vcom-1246) Range 31 downto 32 is
null.

Thanks for the suggestion, though.

Mark 11-25-2009 05:42 PM

Re: converting std_logic_vector to an integer without sign extension
 
On Nov 25, 10:36*am, Mark <marmarjohn...@gmail.com> wrote:
> It doesn't matter to me if FFFF_FFFF is treated as -1 or MAX_INT, just
> that all the bits are in there. *I'd like to get something as C-like
> as possible. *Unfortunately, VHDL treats unsigned ints (naturals) as a
> subtype of integer, and thus are only 31-bits---while C lets you have
> 32-bit unsigned integers (long)). *No problem I thought, I'll just
> treat everything as an integer. *Unfortunately, doing so in a terse,
> warning-free way doesn't seem possible in VHDL.
>
> I'm coming to the conclusion that I'm not going to be able to do a 1-
> liner in VHDL without living with warnings. *I want my conversions to
> be warning free (even if it still works out), so I'm thinking of going
> with the following:
>
> * lower := * * * * c_field_offset;
> * upper := lower + c_field_size - 1;
>
> * if (2**c_field_size-1) > integer'high then
> * * i := to_integer( * signed( slv(upper downto lower)));
> * else
> * * i := to_integer( unsigned( slv(upper downto lower)));
> * end if;
>
> 5-lines instead of 1---but then that's VHDL


FYI, the (2**c_field_size - 1) doesn't work as 2**c_field_size itself
needs to be within the range of integers! I finally punted and just
made it : if c_field_size > 31 then ...

Tricky 11-26-2009 08:52 AM

Re: converting std_logic_vector to an integer without sign extension
 
On 25 Nov, 16:47, Mark <marmarjohn...@gmail.com> wrote:
> On Nov 25, 9:30*am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
>
>
> > On Wed, 25 Nov 2009 06:28:01 -0800 (PST), Mark wrote:
> > >I'm trying to elegantly convert a std_logic_vector(upper downto lower)
> > >to an integer without sign extension using ieee.numeric_std with upper
> > >and lower taking on values from 31 to 0 and with upper >= lower. *I
> > >cannot seem to find a syntax that doesn't generate truncation
> > >warnings, or relies on doing some comparison.

>
> > What's wrong with...
> > * i := to_integer(unsigned(slv));

>
> > It will of course give you warnings if the MSB of a 32-bit SLV
> > is set, because VHDL integer cannot represent anything more
> > positive than (2**31)-1. *That's tedious, but a fact of life.
> > But it should work fine with any slv with between 1 and 31
> > bits, and it will also work with 32-bit SLVs provided their
> > MSB is zero.

>
> > If you want to use signed() so that 32-bit slv's with the MSB
> > set will come out as negative integers (yuck) then yes, you have
> > a small problem with 1-bit values. *How about packing to 32 bits
> > first, and then doing the conversion?

>
> > * i := to_integer(
> > * * * * *signed(
> > * * * * * * std_logic_vector'(31 downto upper+1 => '0') & slv
> > * * * * *)
> > * * * *);

>
> > This *may* give warnings for the null range when upper=31,
> > although it's legal VHDL (I'm pretty sure).

>
> > Finally, why not write a custom function instead of trying to
> > inline the ghastly mess?
> > * function to_uint(v: std_logic_vector) return integer is
> > * begin
> > * * if v'length = 0 then
> > * * * return 0;
> > * * elsif v'length = 1 then
> > * * * return to_integer(unsigned(v));
> > * * else
> > * * * return to_integer(signed(v));
> > * * end if;
> > * end;

>
> > The function also provides you with a convenient place
> > to report application-specific errors and so forth.
> > But most of all it allows you to hide the kruft.
> > --
> > Jonathan Bromley, Verification Engineer

>
> > Verilab *www.THAT_COMPANY.com
> > * end;

>
> Gave
>
> * *i := to_integer( signed( std_logic_vector'(31 downto upper+1 =>
> '0') & slv(upper downto lower) ));
>
> a try. *Got:
>
> * *** Warning: [3] test.vhd(25): (vcom-1246) Range 31 downto 32 is
> null.
>
> Thanks for the suggestion, though.


Why do you have to use the integer type? why cant you just stick with
signed/unsigned? Afaik, you can still do all the same arithmatic on
signed/unsigned, but you have no bit width problems.

Jan Decaluwe 11-26-2009 09:21 AM

Re: converting std_logic_vector to an integer without sign extension
 
Tricky wrote:
> On 25 Nov, 16:47, Mark <marmarjohn...@gmail.com> wrote:
>> On Nov 25, 9:30 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
>> wrote:
>>
>>
>>
>>> On Wed, 25 Nov 2009 06:28:01 -0800 (PST), Mark wrote:
>>>> I'm trying to elegantly convert a std_logic_vector(upper downto lower)
>>>> to an integer without sign extension using ieee.numeric_std with upper
>>>> and lower taking on values from 31 to 0 and with upper >= lower. I
>>>> cannot seem to find a syntax that doesn't generate truncation
>>>> warnings, or relies on doing some comparison.
>>> What's wrong with...
>>> i := to_integer(unsigned(slv));
>>> It will of course give you warnings if the MSB of a 32-bit SLV
>>> is set, because VHDL integer cannot represent anything more
>>> positive than (2**31)-1. That's tedious, but a fact of life.
>>> But it should work fine with any slv with between 1 and 31
>>> bits, and it will also work with 32-bit SLVs provided their
>>> MSB is zero.
>>> If you want to use signed() so that 32-bit slv's with the MSB
>>> set will come out as negative integers (yuck) then yes, you have
>>> a small problem with 1-bit values. How about packing to 32 bits
>>> first, and then doing the conversion?
>>> i := to_integer(
>>> signed(
>>> std_logic_vector'(31 downto upper+1 => '0') & slv
>>> )
>>> );
>>> This *may* give warnings for the null range when upper=31,
>>> although it's legal VHDL (I'm pretty sure).
>>> Finally, why not write a custom function instead of trying to
>>> inline the ghastly mess?
>>> function to_uint(v: std_logic_vector) return integer is
>>> begin
>>> if v'length = 0 then
>>> return 0;
>>> elsif v'length = 1 then
>>> return to_integer(unsigned(v));
>>> else
>>> return to_integer(signed(v));
>>> end if;
>>> end;
>>> The function also provides you with a convenient place
>>> to report application-specific errors and so forth.
>>> But most of all it allows you to hide the kruft.
>>> --
>>> Jonathan Bromley, Verification Engineer
>>> Verilab www.THAT_COMPANY.com
>>> end;

>> Gave
>>
>> i := to_integer( signed( std_logic_vector'(31 downto upper+1 =>
>> '0') & slv(upper downto lower) ));
>>
>> a try. Got:
>>
>> ** Warning: [3] test.vhd(25): (vcom-1246) Range 31 downto 32 is
>> null.
>>
>> Thanks for the suggestion, though.

>
> Why do you have to use the integer type? why cant you just stick with
> signed/unsigned? Afaik, you can still do all the same arithmatic on
> signed/unsigned, but you have no bit width problems.


That is not true: with signed/unsigned you are forced to
deal with bit widths and resizes explicitly, unlike integer.

Given all the pain that comes out of discussions such as this one,
I'd like to point out that with MyHDL, I think I have solved these issues.
In MyHDL, you can use a (constrained) integer with arbitrary sizes,
and the convertor to VHDL will deal with the low-level issues for you.

See:
http://www.myhdl.org/doku.php/why#yo...sion_functions

Background:
http://www.jandecaluwe.com/hdldesign/counting.html

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com

Gerhard Hoffmann 11-26-2009 01:23 PM

Re: converting std_logic_vector to an integer without sign extension
 
On Wed, 25 Nov 2009 23:25:41 +0100, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:


>Yes, I know it's a damned nuisance, but that's what the
>language standard says.


Is there somewhere a standard or near-standard package
for things like u_int64 or s_int128?

Writing a testbed for a 64 bit CPU is a royal pain, and
even if these long ints were composed from the usual 31.9 bit ints,
this should simulate much faster than SLVs, where each and
every single bit has to be kissed individually.


regards, Gerhard



All times are GMT. The time now is 12:49 AM.

Powered by vBulletin®. Copyright ©2000 - 2014, vBulletin Solutions, Inc.
SEO by vBSEO ©2010, Crawlability, Inc.