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-   -   transaction recording (http://www.velocityreviews.com/forums/t702007-transaction-recording.html)

John Smith 10-18-2009 05:33 PM

transaction recording
 
Hi,

Is there any way to record and write transactions to a textfile in
modelsim? I found that is possible for verilog and for systemc but
nothing found for vhdl.

Thanks

Paul Uiterlinden 10-20-2009 03:36 PM

Re: transaction recording
 
John Smith wrote:

> Hi,
>
> Is there any way to record and write transactions to a textfile in
> modelsim? I found that is possible for verilog and for systemc but
> nothing found for vhdl.


What exactly do you mean with transactions?

In ModelSim there is the list window that shows all events on a signal with
the capability to save the results as a textfile in various forms. I'm not
sure if this is what you mean.

And of course there are the standard writeline and report statements to
produce output in a textfile.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

JohnSmith 10-20-2009 08:54 PM

Re: transaction recording
 
On Oct 20, 5:36*pm, Paul Uiterlinden <puit...@notaimvalley.nl> wrote:
> John Smith wrote:
> > Hi,

>
> > Is there any way to record and write transactions to a textfile in
> > modelsim? I found that is possible for verilog and for systemc but
> > nothing found for vhdl.

>
> What exactly do you mean with transactions?
>
> In ModelSim there is the list window that shows all events on a signal with
> the capability to save the results as a textfile in various forms. I'm not
> sure if this is what you mean.
>
> And of course there are the standard writeline and report statements to
> produce output in a textfile.
>
> --
> Paul Uiterlindenwww.aimvalley.nl
> e-mail addres: remove the not.


When I run my design, there is an unexpected value in a signal. I
would like to know who (which statement) is the responsible for that.

Thanks




Mike Treseler 10-20-2009 09:12 PM

Re: transaction recording
 
JohnSmith wrote:

> When I run my design, there is an unexpected value in a signal. I
> would like to know who (which statement) is the responsible for that.


I would trace code and set breakpoints.

-- Mike Treseler

KJ 10-21-2009 12:15 AM

Re: transaction recording
 
On Oct 20, 4:54*pm, JohnSmith <csnew...@gmail.com> wrote:

>
> When I run my design, there is an unexpected value in a signal. I
> would like to know who (which statement) is the responsible for that.
>


Well, that's an easy question to answer. Your design, you're
responsible.

If by 'unexpected' you mean an 'X' or 'U' or something like
that...then use the 'drivers' command. It lists all of the drivers of
a net, helps you find 'unexpected' cases of multiple drivers. Then
try using type 'std_ulogic' rather than 'std_logic' as your basic type
and you won't have to debug to find such errors ever again; the
compiler will flag multiple drivers as an error. Use std_logic only
for the few cases where it really is permissible to have multiple
drivers.

If by 'unexpected' you mean you got 'ABCD' on some data bus rather
than '1234' than you'll have to debug that yourself. Modelsim has all
of the debug utilities (wave, list, source code, dataflow windows,
breakpoints, etc.). Log all of the signals in your design at the
start of sim (command "log -r /*") and you'll have the complete
history of every change that ever occurs on every signal. Can't get
more complete than that.

KJ


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