Velocity Reviews (http://www.velocityreviews.com/forums/index.php)
-   VHDL (http://www.velocityreviews.com/forums/f18-vhdl.html)
-   -   Dynamic Power Consumption Estimates/Comparison (http://www.velocityreviews.com/forums/t701787-dynamic-power-consumption-estimates-comparison.html)

 moogyd 10-16-2009 02:54 PM

Dynamic Power Consumption Estimates/Comparison

Hi,

I am currently comparing soft IP's for use in our next ASIC product.
For the initial comparison, I will use power consumption estimates
from the supplier (mW/MHz).

The issue is that some vendors quote for 90nm, some 130nm and some of
180nm.

Does anybody have a very rough rule of thumb for relative dynamic
power consumption for different technologies.

e.g. On average, 0.5mA/MHz @ 130nm => 4 * 0.5mA/MHz @ 180nm.

Thanks for any comments.

Steven

 gabor 10-16-2009 03:38 PM

Re: Dynamic Power Consumption Estimates/Comparison

On Oct 16, 10:54*am, moogyd <moo...@yahoo.co.uk> wrote:
> Hi,
>
> I am currently comparing soft IP's for use in our next ASIC product.
> For the initial comparison, I will use power consumption estimates
> from the supplier (mW/MHz).
>
> The issue is that some vendors quote for 90nm, some 130nm and some of
> 180nm.
>
> Does anybody have a very rough rule of thumb for relative dynamic
> power consumption for different technologies.
>
> e.g. On average, 0.5mA/MHz @ 130nm => 4 * 0.5mA/MHz @ 180nm.
>
> Thanks for any comments.
>
> Steven

For the same number of transistors (you'd have to check if this is
a good assumption when switching process nodes) the dynamic power
will be proportional to V squared times the gate capacitance. Now
V is easy enough to get (core voltage), but the gate capacitance is
not necessarily something you can derive from the overall geometry.
I would imagine you could get these numbers from your suppliers,
though.

 All times are GMT. The time now is 08:12 AM.