count until read next signal
im trying to create counter where it counts the number of cycles upon receiving the first signal, stops the count on receiving the second one, stores the counts between the two signals and resets the counter immediately after the second sig'event.
i have something like this and i know for sure that it's not the right code:
process (clk, reset, sig)
wait on sig'event and sig = '1';
if (reset = '1') then
count(15 downto 0) <= "0000000000000000";
elsif (clk'event and clk = '1') then
count <= count + 1;
process (sig, t)
for i in 1 to 8 loop
if sig’event and sig = ‘1’ then
t(i) <= sig'last_event; reset = '1';
what bugs me is the 'last_event attribute. so if t = 0, and t1 = n, sig'last_event is n? how does this differ from 'last_active?
i know how to set the counter going, but i have no idea how to stop it. any hints/ideas? thanks!
Would this be code for simulation or synthesizing (hardware implementation) ?
yes it is. is there a requirement to state an upper limit for the counter to stop and reset, because the upper limit cycle counts is each subsequent signal?
Well you better forget about the Last_event attributes - they bound to fail in the matter of synthesizing.
My answer would be - State Machines - Consider this solution:
I'm a little lost. So you're saying that while the clock is ticking, when the signal is '0', the counter will not move until signal reads '1' and falls to '0' (wait_for_Sig_0)
*I'm not sure how conv_std_logic (convert integers into bits) works when it comes to (-1,N). What does "-1" mean?
The counter continues to count while signal is '0', waiting to stop when it hits signal = '1' (wait_for_sig_1).
Once it hits '1' again, the previous count is stored and the counter is reset to count again. This is how I understand the code and it looks like what I have in mind. conv_std_logic is still bugging me.
I originally had process(clk,reset) along with the counter code so I guess that made simulation impossible. I will give it a shot at your code anyway (or modify if necessary) and see it works. Thanks!
edit: I understand the process now (still don't get the conv_std_logic). But another question is how do I store the counts in, say, t : std_logic_vector(7 (for example) downto 0), so I will have t(0) to t(7) each storing the counts as a result of the states. One way I can think of is by FOR loop:
Your bound to fail - putting a loop inside a State Machine (only allowed in a Reset operation).
Take a look at this code - the conversion explained also.
Alrighty. State machines don't seem to churn out my output well, ie. not churning out...
But I managed to come out with this easier code (though I'm going bald from trying to figure out the basics):
Thus I will get t0 = 2, t1 = 1, t2 = 1, t3 = 2
I tried to automate the process with a FOR LOOP by having
Anyway I thought of a way to output the counts is subtraction from previous count. So like, T0 = t0 - 0, T1 = t1 - t0, T2 = t2 - t1,
where tn is counts relative to 0 and Tn relative to Tn-1. Haven't quite figured out the code for that yet.
1) how to output integer counts for each t0, t1, ...t7
2) what's up with conv_integer and std_ulogic? Jeez.
another uneducated idea I have is this:
make an array of sixteen t's such that each holds a 16-bit value of "count"
example: t(0) = 00001100, t(1) = 00000101, etc. After which, I would like to do something like, for example, b(0) = t(0) + t(1)
or essentially, b(i) <= t(i) + t(i+1) (b(15) <= t(15) + t(16) will not exist). Is all this possible or am I just hoping for something non-existent? I tried loops, and I don't wish to continue with state machines. Any others ideas on where I can start?
So I needed to declare a package within the code and the testbench that will allow me to have an array of std_logic_vector's. So 1) is solved. 2) won't be needed for now but would be nice to know more about the problem
Question remains is the last bit. Still trying out a code for that
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