Velocity Reviews - A few VHDL questions

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A few VHDL questions

Hi guys, I'm quite new to VHDL and Verilog. I would like to ask a few simple questions.

1) I read from some internet sources stating that 'file' is an object class. Is it correct? If it is, what is it for and how do we use it?(in general)

2) If I have two architectures in my design, I only need to declare my packages, libraries and entity once right?

3) If I declared a package, which contains say, Q=2. In my design I have 2 architectures. In the first one, I assigned 1 to Q. My question is will this changing of Q's value affect the second architecture? If I were to use Q in the second arch, what will the value be??

4) What is the used of 'generic' in vhdl? I've read somewhere that 'parameter' in verilog does almost the same thing. Can anyone elaborate on this??

Thank you very much!

what is generic in vhdl

hii ....... frnd gereric is a paramiterised variable used to assin width of different vector ..whose value should be initialised during declaration inorder to synthesize it..

Thank you very much![/QUOTE]

how we write vhdl in shorter way in case of dsp applications

hello frnds please any body suggest me to how to write vhdl codes for different dsp applications,and for communication blocks like modulators n demodulators..please giv reply any body ......itz urgent for me...........
advanced thanks to all
...frm praveen