- **VHDL**
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- - **Fir Question**
(*http://www.velocityreviews.com/forums/t692091-fir-question.html*)

Fir QuestionHi all
I am trying to learn a FIR vhdl model and I want to ask the following : 1> The MULTIPLYER architecture is based on the RESULT <= signed(input) * signed(coefficient) What is the signed function needed for ? 2> The data from the ADC how is it to be formed ? The leftmost bit is sign bit ? Thanks Bar Nash |

Re: Fir QuestionOn 22 July, 06:16, "BarNash" <therighti...@gmail.com> wrote:
> Hi all > > I am trying to learn a FIR vhdl model and I want to ask the following : > > 1> The MULTIPLYER architecture is based on the > > RESULT <= signed(input) * signed(coefficient) > > What is the signed function needed for ? > > 2> The data from the ADC how is it to be formed ? The leftmost bit is sign > bit ? > > Thanks > Bar Nash VHDL is strongly typed, so the signed function you see is just a conversion function, probably from std_logic_vector, into a signed type. It wont actually change any of the data. It also implies that RESULT is also of signed type. Typing gives meaning to words - a std_logic_vector is just a collection of bits - it could be a bus of control bits or a data word. The whole point of the signed/unsigned types is it gives meaning to the bus in the code, making it easier for the engineer to understand whats going on. As for the data from the ADC, it will all depend on what ADC it is and whatever it written in the data sheet about what values it outputs. |

Re: Fir Question"As for the data from the ADC, it will all depend on what ADC it is and
whatever it written in the data sheet about what values it outputs." My question is really :What format the ADC output should have since the multiplier treats it as signed ? Thanks Bar Nash "Tricky" <Trickyhead@gmail.com> ×›×ª×‘ ×‘×”×•×“×¢×”:a6091f31-3f48-458d-b0d8-69db6deec1a8@o7g2000yqb.googlegroups.com... > On 22 July, 06:16, "BarNash" <therighti...@gmail.com> wrote: >> Hi all >> >> I am trying to learn a FIR vhdl model and I want to ask the following : >> >> 1> The MULTIPLYER architecture is based on the >> >> RESULT <= signed(input) * signed(coefficient) >> >> What is the signed function needed for ? >> >> 2> The data from the ADC how is it to be formed ? The leftmost bit is sign >> bit ? >> >> Thanks >> Bar Nash > > VHDL is strongly typed, so the signed function you see is just a > conversion function, probably from std_logic_vector, into a signed > type. It wont actually change any of the data. It also implies that > RESULT is also of signed type. Typing gives meaning to words - a > std_logic_vector is just a collection of bits - it could be a bus of > control bits or a data word. The whole point of the signed/unsigned > types is it gives meaning to the bus in the code, making it easier for > the engineer to understand whats going on. > > As for the data from the ADC, it will all depend on what ADC it is and > whatever it written in the data sheet about what values it outputs. |

Re: Fir QuestionOn 22 July, 12:20, "BarNash" <therighti...@gmail.com> wrote:
> "As for the data from the ADC, it will all depend on what ADC it is and > Â* Â*whatever it written in the data sheet about what values it outputs." > > My question is really Â*:What format the ADC output should Â*have Â* > Â* Â* Â* Â* Â* Â* Â* Â* Â* Â* Â* Â* Â* Â* Â* Â* Â* Â*since the multiplier treats it as signed ? > > Thanks > Bar Nash > > "Tricky" <Trickyh...@gmail.com> ×›×ª×‘ ×‘×”×•×“×¢×”:a6091f31-3f48-458d-b0d8-69db6deec...@o7g2000yqb.googlegroups.com... > > > On 22 July, 06:16, "BarNash" <therighti...@gmail.com> wrote: > >> Hi all > > >> I am trying to learn a FIR vhdl model and I want to ask the following : > > >> 1> The MULTIPLYER architecture is based on the > > >> RESULT <= signed(input) * signed(coefficient) > > >> What is the signed function needed for ? > > >> 2> The data from the ADC how is it to be formed ? The leftmost bit is sign > >> bit ? > > >> Thanks > >> Bar Nash > > > VHDL is strongly typed, so the signed function you see is just a > > conversion function, probably from std_logic_vector, into a signed > > type. It wont actually change any of the data. It also implies that > > RESULT is also of signed type. Typing gives meaning to words - a > > std_logic_vector is just a collection of bits - it could be a bus of > > control bits or a data word. The whole point of the signed/unsigned > > types is it gives meaning to the bus in the code, making it easier for > > the engineer to understand whats going on. > > > As for the data from the ADC, it will all depend on what ADC it is and > > whatever it written in the data sheet about what values it outputs. > > hardware multipliers dont really care - they can do unsigned and signed arithmatic. ADC choice is down to whatever you want it to be. If the output is unsigned and you really need signed, you can just put a '0' on the front of it and make it a signed number. |

Re: Fir QuestionThanks
BN "Tricky" <Trickyhead@gmail.com> ëúá áäåãòä:0cb631be-3518-47aa-ba91-94ce30375956@o15g2000yqm.googlegroups.com... On 22 July, 12:20, "BarNash" <therighti...@gmail.com> wrote: > "As for the data from the ADC, it will all depend on what ADC it is and > whatever it written in the data sheet about what values it outputs." > > My question is really :What format the ADC output should have > since the multiplier treats it as signed ? > > Thanks > Bar Nash > > "Tricky" <Trickyh...@gmail.com> ëúá > áäåãòä:a6091f31-3f48-458d-b0d8-69db6deec...@o7g2000yqb.googlegroups.com... > > > On 22 July, 06:16, "BarNash" <therighti...@gmail.com> wrote: > >> Hi all > > >> I am trying to learn a FIR vhdl model and I want to ask the following : > > >> 1> The MULTIPLYER architecture is based on the > > >> RESULT <= signed(input) * signed(coefficient) > > >> What is the signed function needed for ? > > >> 2> The data from the ADC how is it to be formed ? The leftmost bit is > >> sign > >> bit ? > > >> Thanks > >> Bar Nash > > > VHDL is strongly typed, so the signed function you see is just a > > conversion function, probably from std_logic_vector, into a signed > > type. It wont actually change any of the data. It also implies that > > RESULT is also of signed type. Typing gives meaning to words - a > > std_logic_vector is just a collection of bits - it could be a bus of > > control bits or a data word. The whole point of the signed/unsigned > > types is it gives meaning to the bus in the code, making it easier for > > the engineer to understand whats going on. > > > As for the data from the ADC, it will all depend on what ADC it is and > > whatever it written in the data sheet about what values it outputs. > > hardware multipliers dont really care - they can do unsigned and signed arithmatic. ADC choice is down to whatever you want it to be. If the output is unsigned and you really need signed, you can just put a '0' on the front of it and make it a signed number. |

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