Need help initializing LPM_Add_Sub to do Sub
 

Well I got a final Project for tomorrow and the teacher is making us write in VHDL when we never even seen the language, I'm trying to make a subtraction using the LPM_add_sub as he requested (4 bit variables)

I got this using quartus:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY Finalprojsub IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END Finalprojsub;


ARCHITECTURE SYN OF finalprojsub IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);



COMPONENT lpm_add_sub
GENERIC (
lpm_width : NATURAL;
lpm_direction : STRING;
lpm_type : STRING;
lpm_hint : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;

BEGIN
result <= sub_wire0(3 DOWNTO 0);

lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_width => 4,
lpm_direction => "SUB",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);

Each time I try to compile it I get I keep getting "error: Node instance instantiates undefined entity FinalProject"
FinalProject being the name of the project.
Can anyone help me out?