array of STD_LOGIC to STD_LOGIC_VECTOR
I would like to know if there is a way to put a signal STD_LOGIC_VECTOR in an array of STD_LOGIC ??
type X is array(7 downto 0) of STD_LOGIC;
signal Y : X;
signal A : STD_LOGIC_VECTOR(7 downto 0);
A <= Y; -- ou bien Y <= A;
Not clue why you're defining your own std_logic_vector equivalent, but in VHDL the types are incompatible. You will have to assign element-wise like this,
copy: for i in X'range generate
A(i) <= Y(i);
Y(i) <= B(i);
end generate copy;
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