Assignment to output signal from internal signal not istantaneous
I have the following code snippet:
entity driver is
clk_o : out std_logic
architecture rtl of driver is
signal i_clk : std_logic :='0';
i_clk <= NOT i_clk AFTER 100ns;
clk_o <= i_clk;
clk_o is delayed respect to i_clk, is this possible?
Yes, clk_o is assigned a "delta" period of time after i_clk. It's by design of VHDL.
You can get around this by using a proces instead (making i_clk a variable instead of a signal)
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