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-   -   multiplier pipelining (http://www.velocityreviews.com/forums/t669293-multiplier-pipelining.html)

joris 02-06-2009 10:54 PM

multiplier pipelining
 
While letting Xilinx XST synthesising a piece of VHDL, am getting this recommendation:

INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_mult_mult0000 by adding 3 register level(s).

The code contains this:

Code:

when Lmult1 =>
        mult <= v * X"01010101";
                state := L2_2;
when Lmult2 =>
        mult <= subsum * subsum;
        state := L2_3;

(The context isn't too interesting). Anyway, I gave the multipliers their own state to enable resource sharing (which should improving clock already right?)

This isn't a critical program but I'm just interesting at what coding techniques will improve the code.

Hoping you'll help me gain some insight in this. I tried searching on that remark of Xilinx but didn't find much helpful on it - or I might have applied what I thought was meant, incorrectly.
Thanks for any help,

Joris


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