Testbench Question: Internal signals.
 

I am using Aldec 7.1. I wrote a testbench and was able to view the
input and output signals as called out in the Entity of the design
until I wanted to view an internal signal.

My question is how do I view the internal signals such as the
"next_state" of a state machine in the design?

Do I have to assign them to a port in order to view them when I run
the testbench. I.E "Buffered_State <= Next_State;" ????


entity Detection is
port (

.
.
.
Buffered_State : out std_logic_vector;
.
.

);
end Detection;

architecture RTL of Detection is

begin
state_clocked:process(clk) begin
if rising_edge(clk) then
state <= next_state;
end if;
end process state_clocked;
.
.
.

----------------------------------------------------------------
case statements
---------------------------------------------------------------.
.
.
.

buffered_state <= next_state;

.
.
.

end RTL;

However if I rewrite the code to output the "states" to an "out" port,
I get the error message:

Assignment target incompatible with right side. Expected type
"std_logic_vector".

I can understand the reason why it says this since the "type" is
"StateType" for the signal "next_state".

So once again, How do I go about viewing this internal signal?

Re: Testbench Question: Internal signals.
 

Hi,

do you have access to the "signal agent" feature
in your Aldec ActiveHDL version ?

Rgds,
ALuPin

Re: Testbench Question: Internal signals.
 

Yes. I do have that. Never used it before.
~BLF

On Thu, 5 Feb 2009 07:01:09 -0800 (PST), "ALuPin@web.de"
<ALuPin@web.de> wrote:

>Hi,
>
>do you have access to the "signal agent" feature
>in your Aldec ActiveHDL version ?
>
>Rgds,
>ALuPin

Re: Testbench Question: Internal signals.
 

BLF wrote:

> So once again, How do I go about viewing this internal signal?

discover "add wave"
http://support.aldec.com/KnowledgeBa...w=Cmd00101.htm

Re: Testbench Question: Internal signals.
 

On Thu, 05 Feb 2009 10:04:18 -0800, Mike Treseler
<mtreseler@gmail.com> wrote:

>BLF wrote:
>
>> So once again, How do I go about viewing this internal signal?
>
>discover "add wave"
>http://support.aldec.com/KnowledgeBa...w=Cmd00101.htm


Thank you very much. I will give both methods given a try.

~BLF

Viewing Internal Signals in Active-HDL
 

There are at least 2 ways to do what you want to do. The easiest way is to click on the "add signals" icon for the waveform viewer. You will see a hierarchy displayed in the left window of the add signals list box. The root of the hierarchy is your testbench. Click on the next level down which should be the main entity architecture. You should then be able to select the signals you want from the right window. I do this all the time to look at the present state of state machines, etc. You do not need signal agents or the like to do this.

If you need more help let me know or contact Aldec. Aldec is very helpful. They can talk you through the steps to do what you want to do.

Re: Testbench Question: Internal signals.
 

On Thu, 05 Feb 2009 18:47:06 GMT, BLF <b......f2@yahoo.com> wrote:

>
>On Thu, 05 Feb 2009 10:04:18 -0800, Mike Treseler
><mtreseler@gmail.com> wrote:
>
>>BLF wrote:
>>
>>> So once again, How do I go about viewing this internal signal?
>>
>>discover "add wave"
>>http://support.aldec.com/KnowledgeBa...w=Cmd00101.htm
>
>
>Thank you very much. I will give both methods given a try.
>
>~BLF

I got it figured out!!!!

Now I can view the internal states.

There is an example of how to use "signal agent", called "SIGNALAGENT"
located the ALDEC directory "Samples_71".

"C:\My_Designs\Samples_71" is the default location for this directory
when Aldec was originally installed. I used the example as my
template and now it works great!!!


Thanks ALuPin.

Thank you to Mike. I added the "wave" command in my "DO" macro so I
wouldn't have to "right click" and manually add the signal to the
"Waveform Editor", or use the command "add wave" via the command
console to add the signal "next_state" to the "waveform editor".

~BLF