Automating VHDL Simulations in ModelSim
 

Hello everybody,
I'm still pretty new to VHDL and don't really know how to tackle the
following problem:

I want to do a whole bunch of simulations of some VHDL code I've
written, where each simulation run varies in the values of some
constants defined in the testbench. But I don't want to manually change
the values, recompile and start the whole thing over an over again.

Since I don't see a way how to do this in VHDL itself, I tried to write
a TCL script for the simulator (ModelSim). However, ModelSim won't let
the script alter the constants during the simulation, no matter whether
they are defined as 'constant' or 'generic'. I can't define them as
'variables', because the testbench is a structural description and
doesn't contain processes.

Does anyone have another idea? Is this doable with pure VHDL means?
Thanks a lot for any help,
Georg

Re: Automating VHDL Simulations in ModelSim
 

HT-Lab schrieb:
>
> "Georg" <pontifex@sbox.tugraz.at <mailto:pontifex@sbox.tugraz.at>> wrote
> in message news:gm7s9s$sc7$1@newsreader2.utanet.at...
> > Hello everybody,
> > I'm still pretty new to VHDL and don't really know how to tackle the
> > following problem:
> >
> > I want to do a whole bunch of simulations of some VHDL code I've
> > written, where each simulation run varies in the values of some
> > constants defined in the testbench. But I don't want to manually change
> > the values, recompile and start the whole thing over an over again.
>
> Why don't you put your constant values into an array and use a for loop
> to step through the different values?

Hm, isn't a for loop a sequential statement and only allowed inside
processes? As said, I have a structural description of the testbench
without processes.
Or what exactly do you mean? Bear with me, I'm a newbie...
Thanks, Georg

Re: Automating VHDL Simulations in ModelSim
 

Georg wrote:

> Hm, isn't a for loop a sequential statement and only allowed inside
> processes?

Yes. Like this:

...
constant reps : natural := 8;
begin -- process main: Top level loop invokes top procedures.
init;
for i in 1 to reps loop
timed_cycle;
end loop;
for i in 1 to reps loop
handshake_cycle;
end loop;
coda;
end process main; -- that's it

-- from http://mysite.verizon.net/miketreseler/test_uart.vhd

> As said, I have a structural description of the testbench
> without processes.

That doesn't sound like a testbench to me.

-- Mike Treseler

Re: Automating VHDL Simulations in ModelSim
 

Georg wrote:
> HT-Lab schrieb:
>>
>> Why don't you put your constant values into an array and use a for
>> loop to step through the different values?
>
> Hm, isn't a for loop a sequential statement and only allowed inside
> processes? As said, I have a structural description of the testbench
> without processes.
> Or what exactly do you mean? Bear with me, I'm a newbie...
> Thanks, Georg

Is there a reason you are avoiding having a process inside a testbench?
A purely structural testbench seems like not much of a testbench. Where
is the test stimulus coming from? Some component contained in the
structural testbench? Simulator force commands? If the latter, you'd be
better off creating the force statement functionality using high level
behavioral code in the testbench. Doing so is flexible and powerful
since you don't have to stick to RTL synthesizable coding styles. For
instance, here are some trivial examples:

process
begin
wait for CLOCK_PERIOD/2.0;
clock <= not clock;
end process;

process
begin
some_signal <= '1';
wait for 65 ns;
some_signal <= '0';
wait for 10 ns;
some_signal <= 'X';
...

Re: Automating VHDL Simulations in ModelSim
 

"Georg" <pontifex@sbox.tugraz.at> wrote in message
news:gm7v0p$4ud$1@newsreader2.utanet.at...
> HT-Lab schrieb:
>> "Georg" <pontifex@sbox.tugraz.at <mailto:pontifex@sbox.tugraz.at>> wrote
>> in message news:gm7s9s$sc7$1@newsreader2.utanet.at...
>> > Hello everybody,
>> > I'm still pretty new to VHDL and don't really know how to tackle the
>> > following problem:
>> >
>> > I want to do a whole bunch of simulations of some VHDL code I've
>> > written, where each simulation run varies in the values of some
>> > constants defined in the testbench. But I don't want to manually
>> change
>> > the values, recompile and start the whole thing over an over again.
>> Why don't you put your constant values into an array and use a for loop
>> to step through the different values?
>
> Hm, isn't a for loop a sequential statement and only allowed inside
> processes? As said, I have a structural description of the testbench
> without processes.
> Or what exactly do you mean? Bear with me, I'm a newbie...
> Thanks, Georg
>

Yes, you are right, my mistake. However, I would follow the advice already
given and use a process. If you just want to have a quick test then change
your constants into a signal and use the Tcl force command to alter its
value.

Good luck,

Hans
www.ht-lab.com

Re: Automating VHDL Simulations in ModelSim
 

Jonathan Bromley wrote:
> On Mon, 02 Feb 2009 23:33:28 +0100, Georg <pontifex@sbox.tugraz.at>
> wrote:

>> Since I don't see a way how to do this in VHDL itself, I tried to write
>> a TCL script for the simulator (ModelSim). However, ModelSim won't let
>> the script alter the constants during the simulation, no matter whether
>> they are defined as 'constant' or 'generic'.
>
> Yes it can!
>
> When you load the simulation with the [vsim] command, you can use
> the -g or -G options to patch-up the value of generics. In practice
> the likely scenario is that you have a bunch of generics on the
> (portless) top-level testbench, and you simply patch those.

Perfect! This is what I've been looking for! Thank you very much.

> I agree with others that it would be even nicer to use procedural
> code to do it, but if you already have your TB it seems silly to
> rewrite it.

I'll consider that too, but for the moment I'm happy :-)
Greetings, Georg

Re: Automating VHDL Simulations in ModelSim
 

Mike Treseler wrote:
> Georg wrote:

>> As said, I have a structural description of the testbench
>> without processes.
>
> That doesn't sound like a testbench to me.

Well, I have a couple of 'devices under test', which are just entities
and I instantiate them in the testbench. Like that:

------------- Minimal Example -------------
entity test_bench is
end entity test_bench;

architecture TB of test_bench is
constant my_const : real := 1.3; -- this changes in each simulation
signal foobar : std_ulogic := '0';
-- some more signals or constants...
begin

DUT_1 : entity work.my_device(bar)
generic map (
foo => my_const)
port map(...);

DUT_2 : entity work.my_device(bar)
generic map (
foo => my_const)
port map(...);

-- some more DUTs

end TB;
------------- /Minimal Example -------------


If my entire testbench is a process, how can I instantiate my DUTs then?
Greetings, Georg

Re: Automating VHDL Simulations in ModelSim
 

On 3 Feb, 11:27, Georg <ponti...@sbox.tugraz.at> wrote:
> Mike Treseler wrote:
> > Georg wrote:
> >> As said, I have a structural description of the testbench
> >> without processes.
>
> > That doesn't sound like a testbench to me.
>
> Well, I have a couple of 'devices under test', which are just entities
> and I instantiate them in the testbench. Like that:
>
> ------------- Minimal Example -------------
> entity test_bench is
> end entity test_bench;
>
> architecture TB of test_bench is
> * constant my_const *: real := 1.3; *-- this changes in each simulation
> * signal foobar * * *: std_ulogic := '0';
> * -- some more signals or constants...
> begin
>
> * DUT_1 : entity work.my_device(bar)
> * generic map (
> * * foo * * * => my_const)
> * port map(...);
>
> * DUT_2 : entity work.my_device(bar)
> * generic map (
> * * foo * * * => my_const)
> * port map(...);
>
> * -- some more DUTs
>
> end TB;
> ------------- /Minimal Example -------------
>
> If my entire testbench is a process, how can I instantiate my DUTs then?
> Greetings, Georg

Your entire testbench isnt just 1 process - you can have multiple
processes generating the stimulus at the front end that will actually
make stuff happen, and sometimes at least one capturing the output and
dumping it to a log file (or other data file). Normally the process is
a Bus Functional Model (BFM) that generates the stimulus and/or reads
data in from a file. As great as simulators are, I dont know of any
that you could connect to real hardware - it just doesnt run in real
time. So you have to model the input.

You at least have to generate the clock in its own process.

Re: Automating VHDL Simulations in ModelSim
 

Tricky wrote:
> On 3 Feb, 11:27, Georg <ponti...@sbox.tugraz.at> wrote:
>> Mike Treseler wrote:
>>> Georg wrote:
>>>> As said, I have a structural description of the testbench
>>>> without processes.
>>> That doesn't sound like a testbench to me.
>> Well, I have a couple of 'devices under test', which are just entities
>> and I instantiate them in the testbench. Like that:
>>
>> ------------- Minimal Example -------------
>> entity test_bench is
>> end entity test_bench;
>>
>> architecture TB of test_bench is
>> constant my_const : real := 1.3; -- this changes in each simulation
>> signal foobar : std_ulogic := '0';
>> -- some more signals or constants...
>> begin
>>
>> DUT_1 : entity work.my_device(bar)
>> generic map (
>> foo => my_const)
>> port map(...);
>>
>> DUT_2 : entity work.my_device(bar)
>> generic map (
>> foo => my_const)
>> port map(...);
>>
>> -- some more DUTs
>>
>> end TB;
>> ------------- /Minimal Example -------------
>>
>> If my entire testbench is a process, how can I instantiate my DUTs then?
>> Greetings, Georg
>
> Your entire testbench isnt just 1 process - you can have multiple
> processes generating the stimulus at the front end that will actually
> make stuff happen, and sometimes at least one capturing the output and
> dumping it to a log file (or other data file). Normally the process is
> a Bus Functional Model (BFM) that generates the stimulus and/or reads
> data in from a file. As great as simulators are, I dont know of any
> that you could connect to real hardware - it just doesnt run in real
> time. So you have to model the input.
>
> You at least have to generate the clock in its own process.

True, I do that anyway - I just skipped it for this minimal example. In
fact I have two additional entities that generate clock signals and one
process that writes the DUT output signals into a log-file.

But to modify 'my_const', I would have to define it as a variable inside
a process and then I can't use it anymore as a generic input to my DUTs,
right?

Regards, Georg

Re: Automating VHDL Simulations in ModelSim
 

On 3 Feb, 12:39, Georg <ponti...@sbox.tugraz.at> wrote:
> Tricky wrote:
> > On 3 Feb, 11:27, Georg <ponti...@sbox.tugraz.at> wrote:
> >> Mike Treseler wrote:
> >>> Georg wrote:
> >>>> As said, I have a structural description of the testbench
> >>>> without processes.
> >>> That doesn't sound like a testbench to me.
> >> Well, I have a couple of 'devices under test', which are just entities
> >> and I instantiate them in the testbench. Like that:
>
> >> ------------- Minimal Example -------------
> >> entity test_bench is
> >> end entity test_bench;
>
> >> architecture TB of test_bench is
> >> * constant my_const *: real := 1.3; *-- this changes in each simulation
> >> * signal foobar * * *: std_ulogic := '0';
> >> * -- some more signals or constants...
> >> begin
>
> >> * DUT_1 : entity work.my_device(bar)
> >> * generic map (
> >> * * foo * * * => my_const)
> >> * port map(...);
>
> >> * DUT_2 : entity work.my_device(bar)
> >> * generic map (
> >> * * foo * * * => my_const)
> >> * port map(...);
>
> >> * -- some more DUTs
>
> >> end TB;
> >> ------------- /Minimal Example -------------
>
> >> If my entire testbench is a process, how can I instantiate my DUTs then?
> >> Greetings, Georg
>
> > Your entire testbench isnt just 1 process - you can have multiple
> > processes generating the stimulus at the front end that will actually
> > make stuff happen, and sometimes at least one capturing the output and
> > dumping it to a log file (or other data file). Normally the process is
> > a Bus Functional Model (BFM) that generates the stimulus and/or reads
> > data in from a file. As great as simulators are, I dont know of any
> > that you could connect to real hardware - it just doesnt run in real
> > time. So you have to model the input.
>
> > You at least have to generate the clock in its own process.
>
> True, I do that anyway - I just skipped it for this minimal example. In
> fact I have two additional entities that generate clock signals and one
> process that writes the DUT output signals into a log-file.
>
> But to modify 'my_const', I would have to define it as a variable inside
> a process and then I can't use it anymore as a generic input to my DUTs,
> right?
>
> Regards, Georg

Why not just use a generate loop to instantiate the DUTs and processes
X times (in parrallel), that dump out to X log files?

entity my_tb is
generic (
generic_list : int_array := (0, 1, 2, 3, 4);
);
end entity my_TB

....

test_gens : for i in generic_list'range generate

DUT : my_ent
generic map (
foo => generic_list(i);
);

process
file my_log : text open WRITE_MODE is
( "logfile" & integer'image(generic_list(i)) & ".log");
begin
....
end process;

end generate test_gens;