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ed.agunos@gmail.com 01-09-2009 11:57 PM

aggregate assignments
 
we can do stuff like this:

signal some_signal : std_logic_vector(15 downto 0);

some_signal <= (15 downto 12 => '1', others => '0');

BUT.... is there someway we can do something like this:

some_signal <= (15 downto 12 => "1010", others => '0');

Thanks in advance :)

Dave 01-10-2009 01:55 AM

Re: aggregate assignments
 
On Jan 9, 6:57*pm, ed.agu...@gmail.com wrote:
> we can do stuff like this:
>
> * * signal some_signal : std_logic_vector(15 downto 0);
>
> * * some_signal <= (15 downto 12 => '1', others => '0');
>
> BUT.... is there someway we can do something like this:
>
> * * some_signal <= (15 downto 12 => "1010", others => '0');
>
> Thanks in advance :)


How about:

some_signal <= (others => '0');
some_signal(15 downto 12) <= "1010";

Dave

uhu01 01-10-2009 02:07 AM

Hi,

I'm not a VHDL Pro, but the first thing that comes to my mind is something like:

constant zeroes : std_logic_vector(11 downto 0) := "00000000000";
some_signal <= "1010" & zeroes;

Regards,
Andreas


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