Re: Aligned PLL clocks in RTL simulation
Jonathan Bromley wrote:
> We've easily enough got around this for the present
> design, but I'd love to know what all you seasoned
> PLL/DCM users out there do about it. Do you
> introduce small non-zero time delays in all the
> signals crossing the clock domains, so that it all
> works in simulation? Do you treat the various
At least one trick I use with modelsim is to force
clock signal to the DCM outputs from the simulator.
When forced signals are created they work on the same
delta cycle. The same trick can be used also with asics
that contain clock buffers for clock tree roots etc.
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