Velocity Reviews - Simple ALU Implementation

Hi guys,
I have to implement a simple ALU of a 32bit mips..I have already implemented many submodules (adder,multipliers,shifter...) ,that I have to instantiate in the top level module "ALU_TOP". This module receives as input 2 op. (a , b) and a 6bit signal OPCODE on which basis the differents modules are instantiates.

My problem is checking the signal OPCODE directly in the architecture (not in a process , and after begin of arch.). I used that solution because using a process returned me errors reusing the components (and portamaps...)
But now I cannot even check the OPCODE ("If not allowed..")..(I double checked parenthesis or typos..)...

what should I do? Do I have to use a process? But how to use different modules within a process?

I paste the simple part of the code .. and this not work..

Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity alu_top is

        

generic (N:integer:=32);

                

    Port ( A : in  STD_LOGIC_VECTOR(N-1 downto 0);

           B : in  STD_LOGIC_VECTOR(N-1 downto 0);

           OPCODE : in  STD_LOGIC_VECTOR(5 downto 0);

           FUNCT : in  STD_LOGIC_VECTOR(5 downto 0);

           COND : out  STD_LOGIC;

           ALUOut : out  STD_LOGIC_VECTOR(N-1 downto 0)

                          );

end alu_top;



architecture Behavioral of alu_top is



component multiplier_s_u is



         generic(N:integer:=16);



    Port ( A : in  STD_LOGIC_VECTOR(N-1 downto 0);

           B : in  STD_LOGIC_VECTOR(N-1 downto 0);

           SIGN : in  STD_LOGIC;--signed/unsigned selector

           M : out  STD_LOGIC_VECTOR((2*N)-1 downto 0));--output da 32 bit

end component multiplier_s_u;





begin





if OPCODE="000000"  then

cond<='0';

                

end if;



end Behavioral;

ERROR:HDLParsers:164 - "F:/Poli/SDSS/MyProjects/MIPS/alu_top.vhd" Line 50. parse error, unexpected IF

Thanks in advance