Signal Generator code
I've written a vhdl code in xilinx that generates an output waveform
based on the input clock. The problem i'm getting is that the code is
running only for the positive edge of the clock pulse whereas i've
coded it (i hope) to work for both positive as well as negative edges
of the clock pulse.
What i mean is that only that portion of the code is executing when
clock is = 1.
Re: Signal Generator code
On Nov 13, 2:07*pm, coderyogi <zape...@gmail.com> wrote:
> I've written a vhdl code in xilinx that generates an output waveform
> based on the input clock. The problem i'm getting is that the code is
> running only for the positive edge of the clock pulse whereas i've
> coded it (i hope) to work for both positive as well as negative edges
> of the clock pulse.
> What i mean is that only that portion of the code is executing when
> clock is = 1.
> Any help would be appreciated...
In VHDL, you're allowed to write almost any crazy thing you want and
it will simulate. But only a small subset of the things you can
possibly write actually make sense to get mapped into hardware. A
counter (or other flopped logic) that runs on both clock edges is one
of those describable but not buildable things.
The other mistake you've made is that (for simulation only: do NOT try
to build this for real) you should be using a template like this:
if rising_edge(clk) then
... insert rising edge stuff here
if falling_edge(clk) then
.. insert falling edge here
where rising edge is more or less a shorthand for (clk'event and clk =
But again, this is for illustration only. Do not get into the habit of
writing double-edge processes at all. Expunge all references to them
in your mind now. Only do this to show a professor that you "get" some
nuance of how the language works, or if you're writing a testbench
that you know is intended only to run in a simulator.
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